Progressive resource control.

Question and rationale

Can resident SEIGRASM recover one resource while preserving another resource's operation and selected state? Preparation 55810A9141BA completed all 141 accesses, verified direct reset and clock restoration, and retained its acquisition through later PIO activity. Its initial source-off reading changed from 770 to 747; the preceding return changed from 772 to 748. This preparation separates continued acquisition, clock interruption and candidate reset/reacquisition, with PIO stopped and running. The first-use ADC question is part of responsibility for connected resources.

The objective is progressive control of every available component and its connections, project-owned execution wherever programmable, and the physical foundation for Seigsit creation and Hyphos/SeigrOS. Component access, retained observations and electrical establishment have separate evidence requirements. The experiment does not select a universal clock or an event-driven design.

Execution and dependency map

Only this bounded dependency chain is exercised. The reset field's ADC association remains a supported candidate; full reset-domain effects are under investigation. Shared clock ancestry remains unresolved. RP1's second local processor, other controllers and external component connections require their own access and dependency qualification. Documented accessibility is not a physical observation of control.

Method

1. Repeat boot-route establishment, word-by-word upload/readback, RP1 local entry and the six initial PIO transformations. A distinct start command launches the complete resident sequence once. The application processor leaves two seconds without RP1 transactions before collecting the early header.
2. Admit the inactive local timer, verify progress and measure the existing PIO timing reference. Admit the candidate reset held, ADC clock disabled with divider/selector one, PIO stopped with an empty FIFO, and the PIO configuration observed after the prior run's reference. Any mismatch stops before the main mutation point.
3. Enable the ADC clock, confirm active status, release only the candidate reset and inspect ADC defaults. Configure the PIO countdown with divider six and initialize scratch Y to 0xffffffff. No external pin direction or output is changed. Y is an experimental continuity control, not a Seigsit definition.
4. Run six trials in order: stopped/continue, stopped/clock interruption, stopped/reset; running/reset, running/clock interruption, running/continue. Before each trial initialize X to 0xffffffff and recover its stopped snapshot. Select the declared PIO activity. For clock interruption stop and confirm the ADC clock; for reset assert and directly confirm the candidate reset. All three conditions have a 10,000-tick intervention interval. Resume the clock or release reset with direct confirmation.
5. For each trial select source-disabled and then source-enabled input 4. Each selection has readiness confirmation and a 10,000-tick interval, followed by two commanded conversions with bounded readiness polls. Preserve both observations. There are twelve source cases and twenty-four commanded conversions. No first reading is discarded.
6. Stop PIO and recover X. In running trials also recover Y; inspect PIO diagnostics in every trial. This tests endpoint progression and selected retained state. It cannot exclude every transient interruption or establish uninterrupted progression at unobserved instants.
7. On completion or a failure after mutation, stop PIO first, assert and verify the candidate reset, then stop and verify the ADC clock. Check the whole reset bank, divider and selector, and restore admitted PIO configuration. A failed peripheral cleanup operation stops subsequent cleanup. Invalid timing does not prevent an otherwise executable cleanup. Run the second PIO timing reference, restore timer controls, and publish the completed or partial header.
8. Retrieve the entire journal, run the established further PIO transformation trial if the resident sequence completed, retrieve the entire journal again, and recover final PIO/fault observations. Finally hold RP1 RUN low and restore the application-processor pin route.

Source order and conversion count are fixed across intervention types. Reversed intervention order exposes some history dependence but does not remove order confounding or provide independent boot replication. Reset can itself change source state; the contrast therefore concerns the complete recovery sequence. Source-disabled potential is unspecified. ADC clock and reset are changed separately; no ADC register is accessed while its clock is stopped or its candidate reset held.

Native recording and recovery

The local journal contains a 128-octet header, 248 records of 48 octets, and two 128-octet PIO references: 12288 octets total. Every access retains its identity, request, before/after readings, timer endpoints, peripheral outcome, polling count, timer control and interval validity. Records commit after their contents. Polling retains first and last observations, not every intermediate read. Error indications, unchanged readings and incomplete cases remain in the record.

Instruction memory reads cannot verify the stored PIO instruction; its operational consequence is checked through the countdown. Scratch values and timer phase are not restored to their earlier values. Initial/final PIO configuration is compared separately from instruction-memory readback. A changed Y or stopped X can reject coexistence even when every ADC operation completed.

The SD journal occupies sectors 64 through 61439; the FAT boot partition begins at 61440. The image remains 64 MiB. The outer sequence has 11363 operations and reserves at most 45438 recorded sectors. The enlarged bound is enforced by authored persistence instructions, package geometry, the installer and the return reader. Two complete local readbacks test retention; an early header preserves progress before bulk retrieval. A stalled interconnect or failed return path can still prevent recovery.

Declared assessment

1. Reconstruct the local access order, requests, status, timer validity, first failure and cleanup independently from the recovered journal. Assess initial entry, complete local execution, restoration, coexistence and report retention separately.
2. For all twelve cases report both ADC codes, their difference, source selection, intervention and PIO condition. Keep errors and first readings. Reappearance of an initial departure after reset, but not after clock interruption or continuation, supports a reset-associated explanation under these conditions; it does not identify an analog mechanism. Other distributions retain competing source-history, timing and conversion-history explanations.
3. Require observed initial X=0xffffffff, unchanged X in stopped controls and a positive bounded decrement in running trials. Require Y=0xffffffff in all three running trials. Compare diagnostics and the initial/final saved PIO configuration. A mismatch rejects the affected relation without erasing completed acquisition evidence.
4. Compare the two PIO reference rate intervals using their established inner/outer brackets and endpoint quantization. Per-access timing remains raw local ticks; wraps invalidate intervals. No absolute frequency or ERA anchoring is inferred.
5. Require the complete later PIO activity marker and final successful PIO report, alongside identical acquisition content except that marker, for powered-retention qualification. Missing data cannot become a pass.

Physical path toward Seigsit

The identified internal route is source selection to the ADC's internal input, then local observation. Earlier returns demonstrate a source-correlated response; this run tests its controllability through recovery while another resource operates. It does not establish six independently maintained currents or a connection carrying those states.

The RP1 specification lists four external ADC inputs and an internal temperature input. The board route between a controllable electrical source and a suitable independently observable input has not been established. PWM or pad settings alone cannot qualify that connection. The next electrical admission requires the actual source, holding location, connection and observer to be identified, with voltage/current limits and other users of that connection documented. This preparation adds no speculative pin routing or unknown register writes.

Project-owned resident instructions can open access to further resources; which firmware can be replaced, where execution can be installed, and which fixed logic must be bypassed or controlled remain component-specific questions. Seigsit creation must preserve creation before later content and the connected layers needed for its different information relations. This resource-control investigation supplies prerequisites and observations; it does not qualify that creation or transport.

Run procedure

The prepared allowance was 40 minutes powered using the established SD workflow. The larger allowance covers the additional upload verification and two complete journal recoveries. Local acquisition is short; transport and verified SD persistence dominate the observed earlier coordinator duration. The returned completion record establishes the measured coordinator interval; the total powered duration was not independently measured.

Physical results

All declared resource-control criteria were met in this boot. All 248 local accesses completed with valid intervals, covering twelve source cases and twenty-four commanded conversions. No recorded ADC error indication or failed access occurred. The complete outer sequence returned 11,363 operations and 45,438 journal sectors. Its coordinator interval was 1,879.529029 seconds (31 minutes 19.529 seconds), excluding boot-loader time and final record persistence.

Every trial began with X=0xffffffff. It remained unchanged in all stopped controls and decreased in all running trials. The Y value initialized before the trials remained 0xffffffff at every running-trial observation. All six PIO diagnostic observations were clear under the declared mask. Different decrement totals occur over different access sequences; they do not independently measure an intervention-induced rate change.

Both reset trials directly observed 0xf631efff while asserted and 0xf631effe after release. Cleanup restored the complete initial reset bank, stopped the ADC clock, retained divider and selector one, and restored the observed PIO configuration and timer controls. Instruction-memory reads remained zero and do not independently establish stored instruction contents.

All eighteen requested 10,000-tick intervals recorded 10,090 local ticks. Both PIO references returned 14,344 decrements with inner/outer brackets of 86,023/86,095 ticks, reproducing the preceding return. Their divider-normalized interval was [0.9995586322, 1.0005579968]. This connects the observed rates without establishing independent clocks or an absolute time calibration.

The complete acquisition contents matched across both local readbacks except for the expected activity marker, which changed from 0 to 2. The intervening six-case PIO transformation and its final report passed. The application-processor route was restored. Two read-only SD captures matched; boot files and partition geometry matched the preparation. Seven sectors outside the journal differed in filesystem metadata and host-associated directory content; their writer and timing were not established by this capture.

Interpretation and next question

Observed: resident SEIGRASM completed the ADC recovery sequences while retaining the tested PIO state and endpoint progression. It then reused PIO and recovered the earlier journal unchanged. This supplies evidence for coordinated responsibility for connected resources inside RP1. Endpoint observations cannot exclude a brief interruption between observations.

The first source-disabled pair was 769 → 743, a departure of 26 raw codes. Later disabled pairs were all 743 → 744, including both candidate-reset trials. Earlier initial departures were 772 → 748 and 770 → 747. The new return therefore does not support the prediction that either tested reset or clock interruption alone reproduces the initial departure after previous acquisition. Inference: initial conditions or acquisition/source history remain plausible contributors. The reset field may not reset every relevant analog condition; the source-disabled potential is unspecified, and the fixed order remains confounded with history. The cause is unresolved.

The next investigation should establish the electrical connection required by Seigsit creation: identify a controllable source, the location at which its distinct states can persist, a connected observation point and the admission limits of that path. Resident execution now provides an observed way to reach and coordinate resources. Any further first-use comparison should distinguish initial power conditions from later reset and conversion history, retaining the first readings. Repeating identical ADC trials alone cannot establish the missing carrying connection.

Evidence and provenance

Preparation C188B6B4230D. Forty-seven preparation checks passed. SD installation verified 4,096 transfers and two complete readbacks under the volume lock; the card was ejected. The rationale, dependencies, access schedule, declared criteria and source inputs are preserved before execution.

Return 20261007-124923; SHA-256 10892138edb34d2b6140ecf43e3e95b96bd781b052a755a68ecd7c1a303462df. Thirty-two return-assessment checks passed, including altered-record controls that reject lost PIO state, absent progression and missing retained evidence. The preserved preparation is unchanged. The current PC readers admit the declared boot boundary at sector 61440; the return archive preserves those reader sources and the regression checks.

Hardware references

RP1 peripheral specification describes the local processors, ADC inputs and interconnect. RP1 PIO access describes the local control path. The frozen protocol retains the implementation references.