SEIGRASM.

Purpose and execution boundary

SEIGRASM supplies project-owned instructions at the CPU execution boundary. Each implementation contains explicit native opcodes, operands and relative branch displacements. The CPU executes the corresponding bytes. Comments and source numeral spelling are not executed.

The current seed validates a senary representation of native instruction octets, writes those octets into a supplied memory region, performs instruction publication, and calls the resulting code. Publication means making preceding code writes available to subsequent instruction fetch on the executing core. The generated code can read and change memory and return a result.

The common contract is independent of a board name. Its realization depends on the selected instruction set, execution mode and available facilities. Identical input semantics must produce the same specified effect; the physical opcode bytes differ between architectures. Runtime resource discovery can follow a compatible initial entry. These images do not determine an unknown ISA before any compatible instructions have executed.

The target path contains no firmware request, OS service, external compiler, assembler, linker or host-language runtime. The supplied entry is callable machine code. It does not yet establish reset entry, a boot-medium handoff, memory mappings or initial stack storage, and therefore does not establish firmware-independent power-on boot.

ISA implementations and artifact identity

All three implementations are available as .seigrasm sources and directly corresponding native images. Sizes and counts in this chapter are decimal; addresses and offsets marked 0x are hexadecimal.

The image manifest records complete source and image SHA-256 identities. The literal packager copies each AArch64/RV64 encoding as one little-endian four-octet word and each x86 encoding as one octet. It performs numeral conversion and byte serialization only; it does not select instructions, resolve labels or supply target behavior. Branch displacements are already present in the sources.

Senary and execution contract

Source notation

Unmarked SEIGRASM literals are senary. Prefixes 0d, 0x and 0b select decimal, hexadecimal and binary. Thus 10, 0d6, 0x06 and 0b110 denote the same value. The native sources use explicit hexadecimal encodings to expose the instruction fields for ISA verification. Each token denotes a complete native word or octet according to the implementation. // introduces a source comment. Labels appearing in comments are explanatory only.

In-memory senary input

The entry consumes four numeric senary digits per output octet, most significant first. Each input digit occupies one octet whose value is between zero and five; it is not an ASCII character. An input group [1, 1, 0, 3] has value 255 and produces 0xff. The next group [1, 1, 0, 4] has value 256 and is rejected. Four digits are the smallest fixed senary group capable of representing every physical octet.

This grouping is a transport for the instruction bytes required by these CPUs. It does not define a Hyphos value width, Seigbit layer, Seigsit layout or physical six-state carrier. Senary notation and native instruction execution alone do not establish six electrical states.

The source must be nonempty and its digit count divisible by four. Preparation checks required capacity, extent wraparound, intersection and instruction alignment before reading digits. It validates the entire input before writing the first destination octet. A second pass decodes the unchanged source into the destination. A preparation failure returns zero produced octets and performs no destination write or generated-code call.

The root entry returns status and generated-code result; preparation returns status and produced octet count. Publication returns status and generated-code result. The second return value is zero on any reported failure. Root entry returns preparation failure immediately. Direct publication rejects an empty or wrapping executable extent; AArch64/RV64 also reject misalignment. AArch64/RV64 preparation checks alignment before capacity; x86-64 imposes no instruction alignment check. For inputs violating multiple conditions, the first check reached determines the status.

Validation checks the transport and memory extents, not instruction legality or program safety. Supplied opcode content is trusted. Faults, non-returning payloads and concurrent mutation are outside this contract; they are not converted into the status values above.

Entry, memory and instruction visibility

Direct preparation uses the first four arguments; the fifth is used by the root entry. Counts, pointers and return registers follow the physical 64-bit ABI. Generated code must preserve the listed registers and stack, obey the selected calling convention and return normally. Other registers and arithmetic flags may change. No vector or floating-point preservation contract is established.

• The initial execution mode must already match the image. AArch64 and RV64IM require four-octet-aligned entry and generated extent; this RV64 implementation does not support compressed instructions. x86-64 permits an unaligned generated entry.
• Code, input, output and stack must be accessible normal memory. The destination must permit writing and execution. Input remains immutable throughout both passes. Used source, destination, seed and stack extents must be disjoint. Code checks source/destination intersection; the caller establishes the remaining memory conditions.
• AArch64 and RV64 require a 16-octet-aligned incoming stack. For x86-64, incoming RSP modulo 16 is eight, with the return address at RSP; calls into generated code maintain that condition. The x86 seed uses no red zone. Reserve at least 48 octets below the incoming stack pointer for AArch64/RV64 seed frames, or 64 octets for x86-64, in addition to the generated program's own stack use.
• The code does not configure exceptions, interrupts, translation, memory allocation or persistent storage. Any asynchronous handler or concurrent execution must preserve these entry conditions.

Architecture-specific publication

AArch64: read CTR_EL0, derive data and instruction line sizes independently, clean every intersecting data line with DC CVAU, execute DSB SY, invalidate every intersecting instruction line with IC IVAU, then execute DSB SY and ISB before the call. The execution level must permit those operations. This follows the cache publication requirements described by Arm's instruction-cache publication guidance.

x86-64: execute MFENCE, then the serializing CPUID instruction with leaf and subleaf zero, before the generated-code call. CPUID must be available at the entry privilege level. The Intel system programming manual, section on self-modifying code, specifies serialization between code modification and execution.

RV64IM + Zifencei: the decoder uses integer multiplication from M; publication executes FENCE RW,RW followed by FENCE.I. The RISC-V Zifencei specification defines instruction-fetch synchronization on the executing hart.

Each implementation publishes and calls on the same core or hart. Publication to other processors, memory aliases, device memory and concurrent code replacement require additional contracts and verification.

Validation record

The recorded validation reports 42 passing tests, zero failures, using Unicorn 2.1.3 and Python 3.12.4. It identifies all tested sources and native images by SHA-256 and confirms the sources remained unchanged during the run. Thirteen native execution tests run independently for each ISA; three further tests cover source numeral interpretation, invalid literals and native word order.

The execution fixture maps the literal image and input, supplies register and memory preconditions, and starts the emulated CPU at its entry. Observation hooks record instructions and memory writes; they do not replace instructions or provide decoder behavior. Test payloads contain literal native encodings.

These results are software validation of actual native instruction streams. They provide no physical timing, energy, electrical-state, reset-entry or Seigsit-creation measurement. The 42 tests are checks of this foundation, not 42 physical experiments. Earlier apparatus records supply no qualification for these new images.

Bounded queue-change timing

The queue-timing operation appends 131 literal instruction words at byte 2028 of the RP1 SEIGRASM source. Coordinator protocol 4, section 7 carries its 150-cell report: outcome, mode, read/change counts, counter frequency, origin and endpoint, initial/stopped/final observations, attempted-stage flags, three shared-access reports and up to sixteen changed-read pairs. Each pair preserves the immediately preceding FCS and counter bracket together with the changed response and its bracket. Unused cells remain zero.

Observed mode stops at a four-millisecond counter deadline, 262,144 completed FCS reads or sixteen stored changes. Capacity exhaustion preserves the next response in the final-read fields. Quiet mode reads only the counter inside the window. Both modes attempt the guarded stop and bounded readiness check before persistence; a transaction that never completes remains outside the software deadline guarantee. FIFO consumption is a separate stopped operation.

The physical return recovered every timing report. First continuous-entry latency varied markedly, while all nine later-spacing bounds overlapped near 1.31 ms. Those are register-observation brackets, not internal conversion timestamps. The quiet comparison and remaining phase question are recorded with the result.

Reference-derived arrival deadlines

The measured-boundary coordinator and estimator begin at source offsets 4696 and 5172. The estimator intersects every adjacent error-clear unit-arrival spacing bracket from the current reference. Its midpoint selects a prospective deadline; the full interval remains recorded. The coordinator schedules twice that midpoint plus a declared signed margin from the unchanged-divider-write access end.

Section 9 expands to 460 cells. Tail cells 450–459 retain format, side, margin, period bounds and midpoint, rounded margin ticks, multiplier, estimator status and reserved zero. Header cell 1 now holds margin microseconds; cell 2 holds the derived offset after successful estimation. An unusable period refuses intervention with coordinator status 3 and estimator status 1. The existing prepared acquisition and fresh guards remain unchanged.

The physical return completed all 72 conditions. All 48 continuous counts with resolved timing matched the conditional model, and all 24 observed resolved first arrivals matched its cycle prediction. Sixteen close early conditions retained unresolved command position. The result demonstrates this local timing relation for one boot, without establishing internal conversion instants or physical Seigsit transfer.

The independent repeat retained all acquisition counts, timing classifications and observed first-cycle comparisons. Its full report preserves a paired write-relative timing gap and changes in reference counts. This establishes recurrence on the tested apparatus, not general reliability or physical Seigsit creation.

Preparation before acquisition deadlines

The prepared acquisition entries begin at source offsets 3960 and 4436. The coordinator calls preparation immediately after the admitted write intervention. Acquisition clears its report and validates parameters before the counter-only wait, then obtains a fresh FCS guard and enters the existing guarded command body. A missed deadline refuses the command. The full RP1 instruction stream occupies an 8,192-octet region at 0x88000; other instruction streams retain their placement.

Section 9 retains its 450-cell report. Header cell 19 identifies this ordering; header cells 7 and 8 record wait start/end. Acquisition cells 146–149 retain preparation start/completion and the initial FCS read bracket. Acquisition status 9 records a missed preparation deadline; the coordinator maps it to status 5. Unattempted observations remain zero.

The physical return completed all forty conditions. Continuous command start followed wait completion by 2.889–3.611 µs, a 94.7% reduction in median delay from the preceding implementation. All sixteen quiet/observed timing pairs overlapped. Counts, guards and restoration remained accepted.

Write-relative acquisition deadlines

The write-relative scheduling entry adds 124 literal instructions at byte 3464, preserving the earlier entries. After an admitted divider write, it derives the deadline from the recorded end of that access and the rounded requested interval. Report cell 18 identifies this origin; earlier arrival bounds remain available for comparison. A missed deadline refuses acquisition.

The physical return recovered all forty conditions. Quiet and observed continuous counts agreed with the declared model. The wait ended within 0.704 µs of its deadline, but report preparation and admission still preceded the command, whose start followed wait completion by 52.685–65.944 µs. The following prepared acquisition moves that work before waiting and measures the resulting reduction in delay.

Control of the arrival timing origin

The divider-write comparison reuses all existing literal instruction streams. Its six-access intervention performs an exact-prior guarded write of the already-selected divider, retains immediate readback and requires a subsequent exact check. A read-only intervention provides the comparison. The existing journal preserves both access timing and reference/restart arrivals.

In the physical return, all twelve observed continuous write trials changed their alignment relative to the preceding reference and were compatible with integer intervals from the write. All twelve read controls retained prior alignment. This supports a write-related timing origin at both tested settings in one boot. The following write-relative acquisition test retained that alignment in all sixteen observed continuous trials and matched all 32 continuous counts to its conditional model. Internal phase, independent analog freshness and physical Seigsit transfer remain unresolved.

Converter-enable intervention

The enable comparison adds 119 literal instruction words at byte 2988, preserving the earlier instructions. Protocol 4, section 9 records 450 cells: the existing reference, local recovery and restart reports plus a seventy-cell intervention report. Six bounded steps record disable or retained-enable read, a 200 µs counter interval, re-enable or retained-enable read, exact readiness, empty-queue admission and retained-divider admission. Counter brackets surround each access. Failed intervention has its own outcome, prevents restart and returns control for bounded cleanup.

The physical return completed all 40 conditions. Control readbacks confirmed all 24 enable cycles; all twelve observed continuous cycles and twelve retained-enable controls remained compatible with the preceding arrival cadence. This supports retained timing under the tested controls, while its internal mechanism and the physical Seigsit transfer relation remain unresolved.

Measured acquisition pacing

The pacing-divider comparison reuses the existing guarded-access and arrival-referenced restart instructions without changing their opcode words. A stopped, ready and empty admission precedes each selected divider, followed by readback and retained-setting checks. Both B blocks had shorter arrival spacing, and final A returned to the preceding interval. All 32 conditions and restoration completed.

This establishes a reversible component-control response at two tested settings. The observed three/four-entry counts follow restart offset within the measured cadence. Exact pacing law, internal conversion freshness and the physical Seigsit transfer relation remain unqualified.

Arrival-referenced restart

The restart operation adds 109 literal instruction words at byte 2552. It combines the existing timing and stopped-recovery entries into one bounded operation, with no SD persistence between the reference acquisition and the stopped restart. Protocol 4, section 8 records 380 cells: a twenty-cell outcome and timing header, a 150-cell reference report, a sixty-cell local recovery and a 150-cell restart report.

The operation selects the last observed unit occupancy increase as a conservative arrival bracket, requires stopped readiness and successful empty recovery, then waits until the bracket's upper counter plus the requested offset. A missed deadline refuses the restart. Actual wait completion and command-access counters remain separate, so setup overhead cannot be mistaken for the requested delay. Reference failure, unavailable anchor, recovery failure and restart failure have distinct outcomes.

The physical return completed all 28 conditions. Every observed continuous restart was compatible with continuation of its reference cadence, while its command-relative first delay varied. This is a demonstrated timing and component-control relation on the apparatus; no internal phase signal or independently identified analog conversion was observed.

Bounded queue recovery

The autonomous-acquisition implementation adds fifty literal words to the RP1 source for guarded FIFO consumption. It requires stopped control/readiness, checks EMPTY before each read, retains raw status, values and counters, and stops at empty or sixteen consumed entries. Protocol-4 section 6 records the sixty-cell report, including cleared unused cells. The capacity bounds storage and work; it does not assert physical queue depth.

The physical return recovered zero entries in both untriggered conditions, one in each single-command condition, and one then two under continuous acquisition. Continuous mode retained READY alongside START_MANY; stopping therefore requires both start fields clear as well as READY. All recovery, stopped observations and restoration completed. Complete execution is distinct from the multiple-entry criterion, which was not met in the first continuous condition.

Compact component observations

The compact executor initially admitted up to sixteen shared access operations, retaining their reports in RAM before persistence. It clears unused reports, preserves attempted counts and stops at the first failed access. Coordinator protocol 4 persists intent, grouped observations and completion around this local sequence; no SD call occurs between its accesses.

The physical return recovered thirteen seven-operation traces, comprising six commands and seven controls. All six commands recorded READY clear then asserted at the later poll; four changed RESULT and two returned equal codes. Both restorations completed. Counter brackets establish observation timing, without independently identifying analog conversions.

Guarded component commands

The RP1 single-conversion implementation adds access kind 6 for one command with a verified prior register state. A mismatched precondition performs no write. An accepted command is written exactly once and its immediate response is retained; self-clearing fields are not required to equal the written command. Issuance, later readiness and raw result remain separate observations.

The coordinator records protocol 3 with separate ADC and clock cleanup destinations. Completed failures before ADC modification proceed to clock cleanup; failures after ADC modification proceed to ADC cleanup first. Recording failure stops further operations. The physical return recovered one command, a readiness change, a changed result and both restorations. These operations advance direct component control while the existing entry and transport dependencies remain unresolved.

Hyphos bootstrap integration

The Hyphos-defined creation experiment connects raw Hyphos declarations to literal AArch64 SEIGRASM operations for discovery, argument resolution, evaluation and value retention. Hyphos defines construction, qualification, attachment and consumption. The declared sequence executes recovered Hyphos to create a subsequent entity. Source changes and rejected-operation controls test that ownership. The first physical return contains no Hyphos results. The successful retest passed six creation/use cases and seven controls. The unchanged repeat also recorded all 78 operations but correctly rejected all six unavailable creation observations after the first calibration failed. Source execution and recording recurred; successful creation did not. The subsequent all-round procedure schedules creation against each round. Its first boot completed 36/36 cases; its repeat correctly rejected six unavailable inputs, then completed 30 later creation/use cases. Both recovered all 468 source operations. The reference-burst return recovered 108 three/nine/check median summaries computed by SEIGRASM and passed all 36 creation/use cases. The separate nine-reading assessment improved one primary outcome; it did not govern creation. The burst repeat again recovered all 108 native summaries and 468 source operations. Nine-reading calibration recognized 324/324 primary observations while the three-reading candidate lost one calibration round. The existing target calibration also rejected that round: Hyphos completed 30 cases and correctly rejected six unavailable inputs. The subsequent native-supply return recovered six nine-reading calibration records and 432 decisions computed by SEIGRASM. All 324 primary observations, 108 reserved checks, 36 Hyphos creation/use cases and 42 controls passed. Every created entity retained the selected decision timestamp, distinct from the full-reference comparison timestamp. The subsequent carried-action and successive-action investigations retained this native-supply connection in each of two boots.

The source-access investigation identified multi-byte token reads at arbitrary text addresses with stage-1 translation disabled. Declaration and function operations now use bytewise token reads. The corrected source sequence passes explicit alignment checks and completed on the Pi in the retest. The concurrent persistence change prevents attribution of the earlier stop to source alignment alone.

The retest entry completes electrical persistence before source dispatch. The exception-recording operation retains EL2 registers and source progress on an independent stack, then attempts bounded native SD persistence. Recording is permitted only during source execution; nested faults and recording failures stop without retry. Software checks exercised this failure path. The successful physical retest returned normally, so physical exception recovery remains untested.

The chain-length experiment extends continuation to source-controlled stopping within reserved capacities. An optional SEIGRASM chain-control table binds each reservation to its stop record and after-source disposition. Source completion and rejection skip the remaining reservations in that chain. A source that still requests continuation at capacity produces a distinct limit record. The independent reader checks both emitted dispositions and before/after parent relations. The first physical return met all six declared paths, including a third action, completion with unused capacity and a separate capacity stop. Recurrence remains to be tested.

The continuation experiment adds electrical admission from a carried Hyphos decision. Raw proceed source emits continuation, completion or prerequisite rejection; disposition exposes that outcome. The literal AArch64 operation records the disposition before any dependent request. Completion, rejection and invalid dispositions skip both acquisition and subsequent creation. An optional table binds each opportunity to its live Hyphos result; a zero table preserves the earlier admission procedure. These control outcomes belong to the bounded experiment and do not define general Seigsit termination. The first return records eight admitted actions, two completions and two prerequisite rejections, with no acquisition or dependent creation after declined decisions. The first overall experiment criterion was not met because the electrical reference contained two unresolved triples. The unchanged second boot repeated all continuation decisions and passed the full reference criterion, retaining all parent and carrier relations.

The callable opcode seeds for the other instruction sets do not yet implement this Hyphos execution path. Wider Seigsit relations, operative Noesis and SeigrOS installation remain further implementation and measurement work.

Architecture-specific entry and operation encodings can expose the same Hyphos contract within each processor's limits. Additional ISA versions require their own executable implementation and common-contract verification. The Raspberry Pi is the first intended physical apparatus for the AArch64 implementation; its board name does not identify the language or establish results for the other architectures.

Physical qualification criteria

1. Establish and record the initial execution mode, privilege, memory and stack conditions, including the mechanism that transfers control to the native image.
2. Identify the installed source, seed image and payload bytes; recover target evidence of actual entry, decoded output, payload execution and return state.
3. Repeat valid, altered-opcode and rejected-input cases with preserved evidence. Check the resulting memory state against the declared contract and account for the acquisition mechanism.
4. Qualify each ISA on identified physical apparatus before extending an execution result to that implementation. Integrate the first Hyphos payload only with a declared semantic contract and observable acceptance criteria.

The three callable seeds retain their stated emulation qualification. The separate AArch64 electrical return records direct bus access and acquisition; it does not qualify the common seed contract on all three ISAs.

Firmware and silicon access

Replacement mechanisms and dependencies are described in the silicon-access chapter.

Hardware observations

HAL requirements and the native observation contract connect the Hyphos reference to bounded silicon access.

Electrical comparison

Read the six/sixteen-state method and returned results, with direct links to the native journal and independent analysis.

The six-state stability implementation adds held-control scheduling, per-block delay selection and ADC transaction auditing to the same native access path.

The controlled-trigger operation adds explicit trigger omission and status observations before the trigger and after cleanup. Its two callable entries and diagnostic schema are documented with the predefined assessment. The physical return met the declared trigger-dependent status criterion in all 3,888 observations. Omitted triggers retained one raw code across all six requested states. This supports checking status transitions as well as repeated result pairs; it does not by itself qualify fresh conversion or reliable state recognition.

The transition operation combines sequence enumeration and delay/mode selection for matched direct and omitted-trigger acquisitions. The declared protocol assesses retained-result behavior separately from six-state recognition. Untriggered diagnostics retain their raw observations and are excluded from native recognition.

Held-request acquisition adds a literal instruction sequence for longer consecutive observations, using the existing calibration, ADC diagnostics, restoration and native journal operations. Its returned assessment recovered all 3,888 observations with complete diagnostics; the current recognition rule did not meet its coverage criterion.

Calibration renewal and observation duration

The renewal investigation compares the first and current measured calibrations on identical later observations. Cycle rotates reference and validation positions; adaptive acquisition records raw and three-reading median decisions through the existing supervised sample path. Each representation has its own measured calibration. Failed renewal remains unavailable, and validation cannot alter calibration. The first return reconstructed all native decisions. Renewal changed 45 median decisions from unresolved to correct after round 1, with one still unresolved in that paired comparison. Four median decisions remained unresolved across the whole boot; reliable recognition is not yet established. Boot 2 accepted all twelve calibrations and reconstructed every comparison. Renewal reduced unresolved median decisions from 31 to five after round 1, while raw renewal included eight correct-to-unresolved changes. Boot 3 completed the renewal series; full recognition remained unqualified.

Reference separation and recognition tolerance

The gap-calibration operation derives finite acceptance intervals from current reference extrema and neighbouring separation. It shares the existing paired acquisition and recording path. The declared one-third rule preserves an explicit unresolved region; the comparison counts every additional acceptance and wrong assignment. The two prospective returns recognized 864/864 and 863/864 medians, improving fourteen baseline rejections without a wrong assignment. All twelve candidate calibrations retained separated bands. Boot 2 retained one state-1 rejection; physical boundary challenges and independent conversion freshness remain unqualified.

Independent reference procedures

The reference operation schedules separate nominal and mixed-perturbation reference blocks. It applies the same gap rule independently and freezes both calibrations before held-out acquisition. Candidate decision records retain a measured median, recognized identity, availability and calibration provenance. Requested state does not enter the recognition operation.

The reference-derived tolerance investigation tests whether this procedure improves boundary coverage. Its recording contract distinguishes the existing timed acquisition from the subsequent candidate computation. The physical return reconstructed all candidate decisions. Five accepted calibrations recognized all 270 triggered held-out medians; the first calibration rejected overlapping guarded references, leaving 54 outcomes unavailable. Overall improvement was not met. Later references also change calibration age, so the comparison does not isolate reference composition.

The interleaved reference extension adds an explicit order selector to the same operation. It alternates neighbouring reference endpoints, reverses their order and retains the existing calibration and record layout. Configuration schema 15 distinguishes the acquisition schedule. Its two physical returns each accepted all six calibrations, recognized 324/324 triggered held-out medians and retained separation in all 120 perturbed neighbouring pairs. Complete criteria recurred with unchanged instructions and settings. Boot 2 retained a one-code probe margin; single-reading reliability and independent analog freshness remain open.

The reference-order comparison adds selector 2 to the same operation. Both reference blocks now include the tested perturbations; grouped and interleaved acquisition exchange first and second position by round. First-block storage coordinates preserve each state's twelve triples. The same gap and recognition instructions assess both frozen calibrations, with schema 16 recording this schedule. Position-stratified criteria distinguish complete recognition from an advantage associated with acquisition order.

The boundary-response sequence adds selector 3. Six readings at a controlled nominal preceding request are followed by twelve triggered readings at one perturbed target, divided into four recorded medians. Configuration schema 17 retains the existing calibration, recognition and journal layout. The declared comparison evaluates the first and last groups without omitting intermediate readings or adapting calibration from them. The physical return retained all four groups: 287/288 target medians were correct, with one late rejection. Both endpoint groups recognized 72/72 medians; later-group improvement was not met.

Continued boundary acquisition

Selector 4 acquires 54 consecutive readings at each of four fixed boundary requests, retaining the existing sample operation, frozen reference rules and journal format. Six rounds yield 1296 held-out readings and 432 native median decisions. The declared assessment retains every raw excursion and counts correct medians that contain an out-of-band constituent. The two returns recognized 432/432 and 360/432 medians respectively. Boot 2 retained 72 unavailable outcomes after two high reference readings caused state-0/1 overlap; all recorded measurements remain available. Each reading reissues the same requested value; independent conversion freshness remains unproven.

Controlled predecessors

Selector 5 supplies six predecessor readings followed by 66 readings at request 91. The predecessors 104, 92 and 91 occur in all six possible orders across six rounds. All 1188 target readings, 396 target medians and 36 predecessor medians are retained; references and recognition rules remain unchanged. The declared comparison tests initial departures against both controls while preserving later excursions and unavailable classifications. The physical return recovered all 3888 readings and six accepted calibrations. It recognized 394/396 target medians; two later medians after 104 failed. The initial-excess comparison found no consistent upward departure after 104. Acquisition diagnostics passed; independent conversion freshness remains unproven.

Result-read timing controls

The result-read operation selects a programmed GPIO dwell and a minimum successful read duration around the existing PMIC result-register accesses. Voltage requests, ADC trigger/status access and reference acquisition retain their timing. Every altered read restores the original GPIO dwell on success or failure; failed reads are not retried. The declared comparison retains the original path and an elapsed-time control at fixed request 91. The physical return recovered 1568 padded windows, all within the declared range. Two complete round comparisons showed no consistent excursion reduction, and one slower-read median was wrong. Acquisition stopped during round 3 at the CPU-frequency guard. Unperformed comparisons remain unavailable; wire sampling time and independent analog freshness are not established.

Ordered cycle-counter windows

The counter-window operation retains paired architectural counter observations around each cycle-counter endpoint. It follows the existing electrical operation after restoration and pin release, preserves its guard decision and issues no additional PMIC transactions. Separate PMU setup and restoration retain the prior controls. The declared comparison uses 1, 10 and 100 ms intervals with balanced positions. Its brackets address endpoint placement under the stated counter assumptions; absolute clock calibration and the cause of a previous operating transition remain separate questions. The physical return recovered all 36 windows at approximately 1.5 GHz, with narrower endpoint brackets at longer intervals. No acquisition guard stop recurred; electrical recognition remained incomplete.

Conversion and bus diagnostics

The conversion-control experiment adds bounded native observations of released PMIC pins and a trace of the existing ADC register accesses. Its control, quiet and transact entries compare reset before every conversion with reset once per hold, under a common minimum reset-slot duration. Unexpected sampled routing, direction, line state or ADC status stops the sequence and remains recorded. The separate recording, timing and recognition criteria preserve the distinction between digital observations, analog behaviour and exclusive component control.

The physical return recovered 432 complete traces with 100,539 quiet-pin observations and no sampled contradiction. All frozen median criteria passed, while eight held-out raw excursions persisted. Three occurred during explicitly omitted resets, so a reset before each conversion is not necessary for those cases. The cause and independent conversion freshness remain unresolved.

The configuration-retention comparison adds reissue and signals. Enable and channel-selection reissues can be omitted independently after hold initialization. Actual transfers, omissions, sampled CPU pending flags, interrupt masks, exception level and PMIC pin fields remain distinguishable in the native journal. The declared assessment separates policy execution, timing, recognition and the limits of sampled communication observations.

The trigger-relative timing operation adds 185 literal instruction words in phase. It retains the existing access instructions while placing a measured interval before the trigger or after the post-poll status read. Native records distinguish trigger, busy-clear, status and wait stages; timeout cleanup cannot substitute for completion. The physical comparison recovered all 540 acquisitions with valid delay placement and all median criteria passing. Raw exceptions persisted in all three conditions. The measured four-millisecond intervals do not establish conversion freshness or eliminate the excursions.

The retained-result operation adds 339 literal instruction words in retake. It preserves both original pairs, records a scheduled read/cleanup/cleanup-plus-trigger comparison before final cleanup, and retains separate subsequent pairs. Explicit omissions, bounded polls, signal snapshots, failure reasons and measured slots remain in the native journal. All 71 preceding instruction regions are unchanged. The physical return recovered all original and subsequent pairs. Read again and cleanup alone changed no result; adding a trigger changed 96/108, including four exceptional-to-in-band and three in-band-to-exceptional transitions. The journal preserves both observations without selecting a replacement. The unchanged second boot reproduced the update pattern, with 94/108 changed values after triggering and new exceptions. One reference median failed all four frozen rules while all held medians passed. Complete recording therefore remains distinct from recognition qualification.

The trigger-only extension changes eight instruction words to omit the additional cleanup while retaining the trigger, measured slots and native trace. Its physical return changed 93/108 values without that cleanup, compared with 94/108 for cleanup plus trigger and none for rereading. New exceptions occurred under both trigger conditions. All reference medians passed, but consecutive original exceptions left one held median unresolved. The operation preserves that failure independently of its later in-band readings.

The unchanged trigger-only repeat records 99/108 changed values without the additional cleanup, compared with 93/108 previously. New exceptions recur after triggering. All original medians pass in the second boot, despite fifteen exceptional held readings; no held triple contains two exceptions. The first boot's failed median remains part of the comparison. Native records distinguish updates, raw validity and grouped recognition.

Within-bit observations

The sampling operation provides acquisition, register-read and pin entries at byte offsets 0, 4 and 8. It preserves the original received bit and records a second GPIO observation after a configured minimum interval, with separate availability and measured separation bounds. Late clock loss or invalid timing preserves the trace prefix and inhibits further pin transitions. The matched comparison tests sample agreement and the effect of the added work. The physical return retained 324 complete two-sample traces with 10368 agreeing bit comparisons, including traced excursions. This qualifies agreement at those observed instants; continuous line stability and conversion freshness remain unestablished.

Explicit content retention

The content-lifetime investigation adds the experimental value form retain content, invoked by a raw Hyphos preserve definition. The AArch64 retention operation returns integers by value or copies text bytes into the caller's bounded arena. Text is limited to 8192 octets in this implementation. Objects are rejected. Insufficient capacity or invalid input restores the allocation and source cursors and publishes no value.

Ordinary values keep their existing borrowed-source behavior. Retained bytes remain available until their arena is released; this operation introduces neither reclamation nor persistence. The generic operation contains no Seigsit field names or construction rules. Existing Hyphos definitions create the entity, attach the retained content through its carrier, recover it and define subsequent creation. The first physical return recovered the original text and raw Hyphos after supplying-buffer replacement, and execution of retained Hyphos created an empty successor. Both retention cases passed. One electrical-reference mismatch prevented complete experiment acceptance. Both retention cases also passed in both logging boots, with the logging phase after restoration; electrical exceptions persisted.

The native logging investigation adds flat-object encoding and SD retrieval. Raw Hyphos defines the entry and checks the recovered numeric fields; SEIGRASM transfers canonical values without storing process addresses. Native retrieval checks each sector's run identity, position, senary encoding and integrity, then republishes the object only after a complete canonical comparison. The experiment clears the temporary entry arena and encoding buffer before retrieval. The first transport is bounded to eight integer or text fields and sixteen-octet names/text. The two physical returns each recovered and consumed all five entries after temporary storage clearing, with every capacity control passing. This establishes recurrence of within-boot retrieval for those cases. Each boot consumed its own journal; recovery after restart or power loss remains untested.

Seigr time: measured intervals

The timing foundation relates observations to an identified measuring source. Earth rotation angle (ERA) is the proposed astronomical reference. ERA and local elapsed duration require an explicit reference relation: a counter started during boot does not establish an astronomical date. The IERS definition, section 5.5.3, relates ERA to UT1; SOFA, section 3.5, describes the variability of Earth rotation. ERA anchoring and physical uncertainty calibration are not implemented in this measurement increment.

The AArch64 time instructions read the physical counter with an ISB before and after the reading. The accompanying CNTFRQ value is reported configuration. It does not independently measure oscillator frequency. Arm's Generic Timer documentation defines the counter and ordering requirements. This operation uses direct instructions and makes no firmware service request.

Zero elapsed ticks remain distinguishable from an unavailable duration. Counter wrap, reset and power-off time are not inferred. One boot supplies the current source segment; these instructions do not yet implement migration between timing sources or discovery of timing resources on other ISAs. The unfinished reference time.monotonic advances by a fixed duration per call when its timer is unavailable. This increment instead leaves elapsed duration unavailable unless endpoint evidence supports it.

The acquisition wrapper preserves six values per attempted observation: start, end, initial frequency, final frequency, interval status and elapsed ticks. It retains the existing electrical return status separately. The bracket includes supervision, selection, settling, ADC transactions and any calibration or recognition performed by that call. It cannot be interpreted as the ADC conversion duration. Records are carried through the existing native senary SD journal and reconstructed by the independent reader.

Cadence uses ordered counter observations to impose a declared minimum wait before timed acquisition. The spacing experiment balances 0, 5 and 20 ms across validation triples while references remain unspaced. The ADC operation now orders its existing trigger-slot, status and result-read timestamps with ISB before and after each retained counter read. Both spacing returns retain 3888 valid whole-call intervals and 27216 ordered ADC observations each, with every prescribed spacing met. Candidate recognition was 288/288 in each condition and boot; longer spacing showed no observed recognition benefit. Individual raw-reading overlap and independent conversion freshness remain unresolved. Timing integrity and recognition are assessed separately.

The ordered timing comparison retains the voltage requests, reference renewal, three-reading medians and separation rule of the two preceding returns. Those returns yielded 864/864 and 863/864 correct candidate decisions. Ordered intervals can establish when an unresolved observation was acquired and when subsequent observations returned inside a band. They cannot establish the physical cause of an excursion, independent conversion freshness or an improvement in absolute clock accuracy. Added execution and recording overhead are apparatus differences.

Instruction checks exercise exact arithmetic, ordering and unavailable durations. Integrated checks exercise acquisition, unchanged recognition, recording, failure paths and rejected record mutations with supplied counters and device responses. The two returned timing runs each recovered 3888 valid ordered intervals, with 864/864 and 863/864 correct candidate medians. Boot 2 records one rejected median followed by a correct median 104.914 nominal ms later between ordered endpoints. Timing integrity recurred; complete recognition did not. ERA anchoring and absolute clock accuracy remain unqualified.

Challenge dispatch selects a prime request, an omitted-trigger request, a triggered update and a bounded request perturbation, then delegates to the existing timed acquisition. It retains the ordinary classifier output even for deliberately omitted triggers so that a valid identity cannot be confused with conversion freshness. The freshness and boundary protocol specifies the schedule, evidence fields and distinct qualification criteria.

The balanced schedule extends the same dispatch with a selector and computes each probe offset from round and trial position. All six offset permutations occur while acquisition, calibration, recognition and recording retain their existing operations. The physical return recovered the declared schedule with 504/504 unperturbed medians correct and 36/144 perturbed medians rejected. These outcomes preserve the distinction between nominal recognition and boundary robustness.

Execution inside RP1

The local-execution sequence combines authored AArch64 boot-bus instructions, a Cortex-M3 program with its own polled return channel, and four PIO instructions. It establishes and verifies pin routing, checks every uploaded word and the unstarted marker, requires a run-bound local-entry report, then requests six stopped/running PIO comparisons.

The first preparation stopped before reset because the required routing was absent. The configured-route return completed all 833 operations, verified all 228 uploaded words and recovered all six expected transformations. Two full local reports match; routing restoration and retained SD controls pass. This establishes local SEIGRASM execution and PIO control on this apparatus in one boot. Physical Seigsit creation and control of the remaining cluster components require further evidence.

Anchored waits and longer action groups

The source and conversion history experiment adds access kind 7 to wait from an earlier same-group report end. The ten-cell report retains status, kind, anchor, offset in microseconds, deadline, zero device writes, zero device reads, counter frequency, entry and exit. Status 2 means the deadline was already reached on entry; invalid definitions produce status 3. Descriptor binding and independent recovery verify the anchor relation. The compact executor now admits 1–128 accesses, retaining explicit allocation, attempted count and stop-on-failure behavior.

The physical return completed sixteen 120-access groups and all 64 anchored waits, with no missed deadline. All four cases in every block met both predeclared interval-overlap checks. This establishes the recorded scheduling capability on this apparatus; exact internal electrical timing remains unresolved.

The preparation time and conversion activity return uses the same instruction streams for sixteen 124-access groups, two deadlines per case and 128 completed anchored waits. All 64 cases retain three references, a commanded or read-only conditioning slot, and three probes. Every block meets the three declared timing-overlap checks. This extends observed scheduling and recording coverage while preserving the distinction between software access brackets and internal electrical events.

Internal source control

The source-response experiment uses existing guarded writes, readiness waits and compact recording to change the RP1 sensor-source control while retaining the ADC channel and conversion settings. Each sixteen-access group records a reference, the source intervention, an untriggered result and two subsequent commanded observations without intervening SD access. The returned boot completed 48 conditions with consistently directed responses to source changes and small unchanged-source differences. This is evidence for the observed control relation; six calibrated physical states and Seigsit creation remain open.

The subsequent departure-and-return experiment uses the same instruction streams for two source writes and three observations per group. All 72 returned sequences completed; matched controls retain a small immediate return residual for one direction. Both writes and actual command intervals remain independently recoverable.

The balanced return-delay and acquisition-order comparison completed 144 sequences and 432 conversions. Its small residual does not recur consistently across both pair orders; the first pair also exposes sensitivity to separate local references. The source and conversion history comparison then completed 64 cases in sixteen four-case blocks. All untriggered results retained the preceding reference; repeated references and first-return contrasts expose a smaller acquisition-history relation. Its internal cause remains open, within the wider objective of direct control across the silicon cluster.

Local time relationships

The local timing instructions admit and observe SysTick with interrupts disabled, configure an authored PIO countdown, preserve its X state across pauses and divider changes, and record processor-timer brackets around PIO control. Timer admission and PIO progress remain separate outcomes. A wrap indication invalidates the affected interval. Saved configuration is restored; the old timer phase is not restorable.

The physical return completed 36 cases: 12 unchanged stopped controls, 24 progressing cases, valid intervals and 35 continuous case boundaries. All divider-normalized bounds include 1; reversed order reproduced each count and interval length. Two recovered journals agree except the declared marker for a completed subsequent PIO trial. These are local relative-time observations. Absolute accuracy, independent oscillator ancestry, long-duration stability and ERA anchoring remain unqualified.

Authored AArch64, Cortex-M3 and PIO encodings produce the executable path. PC tooling packages those instructions and independently assesses the records. Boot firmware, RP1 ROM entry, inherited clocks and the existing return transport remain apparatus dependencies. Method and control boundaries.

Timed local acquisition

The local acquisition instructions use the observed processor-source SysTick with interrupts disabled. They execute the bounded source-access schedule, preserve 48-octet records with separate access and timing outcomes, and record PIO references before and after acquisition. Invalid timing stops acquisition; owned cleanup remains bounded. Each reference preserves timer brackets, countdown endpoints, diagnostics and restored PIO configuration.

The physical return records all eight source cases and 24 commanded conversions. All 135 committed intervals are valid and both PIO references agree. The reset SET alias returned zero at the first cleanup operation; its expected-one comparison stopped before direct reset verification. Matching recovered reports do not qualify the declined later PIO trial. The direct-reset comparison then completed all 141 accesses with valid timing: alias reads remained zero, the direct register confirmed restoration, the ADC clock stopped, and acquisition contents survived further PIO activity. This qualifies restoration and powered retention in that return while preserving the same target instructions.

The progressive resource-control return completed 248 local accesses under ADC continuation, clock interruption and candidate reset, with PIO stopped and running. Running trials retained selected Y state and recorded X progression. Both timing references and cleanup passed; the journal survived further PIO use. The resident resource-control instructions and distinct retrieval commands extend the local journal to 12 KiB. These observations qualify the tested resource coordination; the physical carrying connection required by Seigsit remains unresolved.

Resident acquisition and observation retention

The prepared resident extension executes bounded read, write/verify, expectation, polling and cycle-wait operations on RP1 core 0. Each completed operation commits its request, before/after observations, counter bounds, status and polling count to a local SRAM journal. Counter availability, progress and restored control values are recorded. The local counter is not assigned a calibrated frequency.

The preparation contains eight balanced source conditions, 24 commanded conversions and eight untriggered observations. The application processor initiates acquisition once and recovers the local journal afterward. A subsequent PIO trial tests retention of the acquisition records. The physical return repeated local entry and the initial six PIO cases, then recorded DWT control 0x4f000000 and stopped before ADC access because the cycle counter is unavailable. Both complete resident reports match; subsequent PIO activity was declined and its retention criterion remains untested. The later local-time comparison records an available timer and PIO rate relation; the timed acquisition return completes the source cases and identifies a cleanup verification boundary, resolved in the subsequent direct-reset comparison.

Reset-bank-zero field zero is an explicit ADC-selection hypothesis. Clock admission, selective reset release, register defaults and conversion behaviour test that prerequisite before the source comparison. A partial return remains a partial result. Powered instruction and observation retention does not establish physical Seigsit states or power-loss persistence.

Prepared experiment and declared assessment