RP1 clock control.

Question and rationale

The preceding clock-before-access experiment wrote 0x00000800 and read back 0x10000800. Its whole-register comparison rejected the additional field and its restoration guard refused to clear the request. Link and RP1 identity remained readable. The next question was whether that additional field followed clock control reproducibly while access and restoration remained usable.

This experiment isolates clock control before further ADC access. It establishes a component-control prerequisite for the investigation of physical Seigsit creation and transport.

Method

Retain route initialization and require initial clock CTRL=0, DIV=1 and SEL=1. Execute three enable/disable cycles. For each phase, record the initial word, exact requested word, immediate readback, read/write counts and counter brackets. Wait at least one millisecond, then individually read CTRL, DIV, SEL, root link and RP1 identity. Repeat the unchanged request to test whether a further write is omitted. End with a guarded clear, a wait and final control/access checks.

SEIGRASM access kind 5 separates writable control mask 0x0800 from observed-field mask 0x10000000. Write only the exact requested control value. Preserve the full raw response; exclude only the declared observed field from readback equality and reject unrelated changes. The observed field is never asserted in a written word. This contract does not establish its RP1 meaning.

The frozen schedule contains 114 operations. Enable/disable requests are at indices 51/60, 69/78 and 87/96; the final sequence spans 105 through 113. Each operation has intent, report and completion records. No ADC register access or acquisition descriptor is scheduled.

Assessment criteria

Evaluate recording completeness, control acceptance, observed-field relation and restoration separately. Sequence acceptance requires every declared control/access check and final enable clearing. The extra field is retained as an observation; agreement with the request is not an acceptance condition. A complete record does not prove oscillator activity, frequency or ADC usability.

A completed failure after the first enable attempt branches to final observation/restoration while retaining the first failure. Unrecognized control fields refuse a write. A recording failure stops further operations. Counter deadlines cannot interrupt a bus transaction that never returns.

Preparation and dependencies

Candidate 008929294B07 uses literal AArch64 SEIGRASM instructions. Nineteen supplied-response execution checks passed before installation, covering ordinary, delayed, absent and persistent field responses, unrelated changes, redundant requests and restoration failures. Both full installation readbacks matched the image. The frozen protocol specifies a two-minute powered interval.

PC tooling packages instructions and independently reads evidence. Existing ROM/EEPROM entry, AArch64 execution, processor counter, SD and PCIe transport, retained bridge power/reset/reference-clock setup and existing RP1 firmware remain apparatus dependencies. The ADC routine remains in the image without a callable descriptor. This run does not replace firmware or create or transport a physical Seigsit.

Results

All 355 consecutive records and 114 operations were recovered with accepted completion. Every enable wrote 0x00000800 and immediately read 0x10000800. Every disable wrote zero and immediately read zero. Later observations agreed in all six phases.

There were exactly six clock-control writes. All six repeated unchanged requests performed one read and no write. All phase observations retained DIV=1, SEL=1, root link 0x0003e0b0 and RP1 identity 0x20001927. The third disable cleared CTRL. Final restoration therefore returned status zero with no additional write; its later CTRL observation was zero and the final gate passed.

The seven explicit one-millisecond waits in the clock sequence lasted at least 54,000 ticks each at the reported 54 MHz counter frequency. Immediate update routines spanned 163–165 ticks, approximately 3.02–3.06 microseconds. Later CTRL observations began 232.592–233.792 milliseconds after those routines ended, including journal persistence. These intervals do not measure oscillator settling or the instant at which the additional field changed.

The coordinator recorded 756,919,706 ticks, 14.017032 seconds, from entry to its terminal snapshot. Terminal SD write/readback and boot-loader time are outside that interval. The terminal report contains index 113, status zero and 114 completed operations. No ADC trial was attempted.

Acquisition and recording integrity

Initial PC reads failed with Windows CRC error 23 at the partition table, first journal sector and boot partition; Windows also reported disk event 7. A retry after reconnection still failed. The subsequent acquisition recovered two identical complete 64 MiB reads. Its partition layout matched preparation. The failures do not establish whether the card, reader or connection caused them, and successful recovery does not establish general media reliability.

Independent decoding verified record identity, checksums, ordinals, senary fields, operation order and terminal counts. All 32,349 unused reservations matched preparation. The MBR, executable and boot configuration were unchanged. Seven other boot-volume sectors differed and a System Volume Information directory was present; the writer and timing of those changes remain unestablished. The SD was not rewritten during acquisition.

Interpretation and next investigation

The additional field followed the control request through all three cycles in this boot. Its appearance did not prevent a subsequent disable, access to RP1 or final control restoration. Separating that observation from writable control removed the specific whole-register rejection encountered in the preceding experiment. No unrelated CTRL field appeared in these recorded phases.

The result supports a repeatable control/readback relation under this sequence. The extra field's full semantics, oscillator activity and recurrence across independent boots remain unconfirmed. No ADC register was accessed, so neither usable conversion nor the earlier 0xdeaddead response is resolved.

Next investigation: retain the observed clock-control contract and bracket a single ADC control/status read with clock, root-link and RP1-identity observations. Preserve the first response and attempt guarded clock restoration. If access remains valid, a subsequent bounded conversion sequence can test acquisition. This isolates the first ADC access before increasing the number of operations or moving toward Seigsit use.

Evidence and provenance

Preparation identity: 008929294b075f183768c45f66ec23603b0763b041441df6754247919e706a8b. Returned capture SHA-256: cf6f8d5a88ff46af06a3e31a036ea4d0081161052ef55cea4e23dd1fe5882faa.

Twenty return-analysis checks cover the four preserved RP1 returns, including independent record reconstruction, transition/readback relations, redundant-write counts, final restoration, altered control criteria and incomplete terminal evidence. The terminal record cannot establish its own target readback.