RP1 clock-before-access.

Question and rationale

The preceding experiment established the RP1 route but read ADC registers while their clock was disabled. ADC reads and subsequent clock reads returned 0xdeaddead. This experiment tests clock-before-access initialization and records controls around the first ADC read, before attempting autonomous acquisition. Component control remains a prerequisite under investigation for physical Seigsit use.

Method

Retain route initialization, read clock CTRL/DIV/SEL separately, and admit only initial CTRL=0 and DIV=1. Write the enable field using mask 0x0800. The access operation requires the entire readback to equal the requested word. If accepted, wait one millisecond, verify clock settings, bracket the first ADC CS read with root-link, root-command, RP1-identity and clock observations, then perform fourteen stopped/single/continuous trials.

Keep the clock enabled during ADC restoration checks. Following normal completion or a completed failure after the enable attempt, record root link, RP1 identity and clock CTRL. The final guard allows clock restoration only from CTRL=0 or 0x0800; any other value produces status 4 without a write. The terminal report preserves the first failure even when this final operation also refuses.

Assessment criteria

Assess recording completeness, route access, clock validation, ADC acquisition and restoration separately. The frozen sequence contains 84 operations and at most 349 record sectors. Operation 49 enables the clock; operations 80 through 83 form the final observation/restoration sequence. A failure at 49 jumps to 80 and leaves operations 50 through 79 unattempted. Successful recording does not establish successful acquisition.

Preparation and dependencies

Candidate 8177E25C6B65 uses literal AArch64 SEIGRASM instructions, with PC packaging and evidence readers. Sixteen supplied-response execution checks passed before installation; both full SD readbacks matched the image. The frozen protocol specifies one two-minute boot.

ROM/EEPROM entry, AArch64 execution, the processor counter, SD and PCIe transport, retained bridge power/reset/reference-clock setup and existing RP1 firmware remain apparatus dependencies. The experiment neither replaces component firmware nor establishes physical Seigsit creation or transfer.

Results

175 consecutive records were recovered with a complete terminal refusal. The journal contains 54 completed operation reports: indices 0 through 49, then 80 through 83. No ADC register access or acquisition trial was reached.

The update operation recorded 170 ticks between its start and end counters at a reported 54 MHz, about 3.15 microseconds. This brackets the update routine; it is not a measurement of oscillator settling. The coordinator advanced from 1,931,521 to 382,442,205: 380,510,684 ticks, approximately 7.046494 seconds, excluding terminal SD write/readback and boot-loader time. Longer waiting would not advance this terminated invocation.

Both read-only captures matched. All record checksums, ordinals, senary fields, operation order and terminal counts passed independent decoding; the remaining 32,529 reservations were unchanged. The MBR, executable and boot configuration matched preparation. Seven other boot-volume sectors changed and a System Volume Information directory was present; their writer and timing are not established.

Interpretation and next investigation

The immediate stop is explained by the implemented comparison. Readback contains the requested 0x0800 enable field. Its sole difference from the written word is 0x10000000. Whole-register equality converts that difference into status 1, and the restoration guard rejects the same field. This does not establish a failed enable request, a broken route or an ADC exception. It also does not measure whether the clock is oscillating.

The RP1 clock implementation identifies enable with mask 0x0800 and tests that field when reporting clock state. The consulted source does not define the additional field. Raspberry Pi's RP2350 clock definitions use 0x10000000 for a read-only enabled indication. This is a hypothesis-generating comparison with a different component, not an established RP1 definition.

Next investigation: the clock-control experiment characterizes ADC-clock control without accessing the ADC. Separately define the writable enable request, its readback acceptance and the unexplained field observation. Preserve all raw values and reject unrelated changes. Record a bounded enable/read/disable/read sequence with link, identity, divider and selector controls; determine whether the additional field reproducibly follows enabling and clearing. Restoration must distinguish writable configuration from returned status. The supplied-response model must include the observed 0x10000800 response and delayed transitions before preparing a new image.

This boot did not reach the test of whether enabling the clock makes ADC access usable. The earlier 0xdeaddead response, autonomous conversion, freshness and physical Seigsit formation remain unresolved. The useful result is a localized control/readback mismatch and retained access to RP1 after it.

Evidence and provenance

Preparation identity: 8177e25c6b65f8b2e7cd1512bce5bdc0582936ab3bc580e7615ab8eb05b57af3. Returned capture SHA-256: 1b105b794f63be9a2993071d407996afcc463538305a210e207ae453e1d416ab.

Fourteen return-analysis checks passed across the three preserved RP1 returns. They include independent raw-field decoding, refusal before ADC access, the skipped operation range, the zero-write restoration guard, preservation of the first failure, tampered criteria and missing terminal evidence. A terminal record cannot prove its own target readback.