Local execution with configured routing.

Question and rationale

Can SEIGRASM establish the RP1 boot connection, take responsibility for local execution, and use that execution to control PIO? The preceding return stopped before reset because SDA/SCL remained in GPIO mode. This preparation explicitly selects and verifies their documented controller functions before continuing the local-execution sequence.

The objective is control over every silicon component and its interconnections, replacement of inherited firmware dependencies, and the physical foundation for Hyphos, SeigrOS and the Seigsit. Local execution reaches RP1 resources whose control registers are unavailable through application-processor PCIe access. This experiment uses the internal PIO transmit/receive path; multilevel electrical transport remains a further requirement.

Method

1. Inventory AON pin and BSC state. Admit the observed GPIO routing, SDA/SCL inputs, RUN output/high and a disabled, idle controller. Change only the SDA/SCL selectors to function 4, verify the complete mux word, and recheck the connection before reset.
2. Assert RP1 RUN for 100 ms, release it and wait 100 ms. Access boot address 0x43; release SYSINFO reset only, check component and watchdog identities, and record all three reset banks.
3. Upload the authored Cortex-M3 instructions, empty report, six run-bound challenges, four PIO instructions and fault vectors. Verify all 228 four-octet words. Require the unstarted marker to remain zero before issuing the verified watchdog entry sequence.
4. Recover the local entry report through the program's own I²C5 service at 0x44. Require the marker, entry phase, zero status/case count, processor/core identity and first two run challenges before requesting PIO.
5. Run one PIO trial. For each challenge, record one queued transmit value and an empty receive FIFO while SM0 is stopped. Enable SM0, recover the transformed value, stop it and record the result. The four PIO instructions are PULL BLOCK; MOV ISR, ~OSR; PUSH BLOCK; JMP 0.
6. Recover the 256-octet report twice, hold RUN low, restore the original SDA/SCL selectors, record final pin/controller state and park the application processor.

Each operation has a native intent, result and completion record. Before a RUN attempt, cleanup restores only the route; afterward it holds RUN low before restoring the route. Failed cleanup or recording stops subsequent work. The schedule contains 833 operations and at most 3,320 journal sectors. Stopped controls wait 10,000 local iterations; completion polling is bounded at 10,000 reads. These bounds do not define calibrated durations.

Declared criteria

Acceptance requires verified routing and preservation of adjacent fields, complete upload readback, the zero unstarted marker, a matching local-entry report, all six stopped/enabled PIO comparisons, and two equal complete reports. Final routing must match its initial word, direction control and SD outputs must remain unchanged, and RUN must match the cleanup path. Missing observations cannot satisfy a criterion.

Preparation and acquisition

Preparation 6C3BE4F5CBF8, protocol rp1-local-pio-2, contains 27 frozen source inputs. Twenty preparation checks passed, exercising authored instructions against supplied responses and the preceding capture's reader regression. The broader targeted suite passed 48 checks. Installation verified 4,096 chunks and two complete readbacks before ejection.

The prescribed powered interval was five minutes. The returned 64 MiB region was acquired twice using read-only access; both hashes agree. The execution interval below comes from the target's architectural counter. Total powered duration and physical boot count were not independently measured.

Return: local execution and PIO control

All 833 operations completed successfully and all 3,320 journal records were recovered. The 819 boot-bus transactions report no controller error, timeout, short transfer or comparison failure. Independent reconstruction confirms the complete sequence and all 228 upload readbacks.

In every case, stopped FSTAT is 0x0e000f00 and FLEVEL is 1: one transmit entry and no receive entry. After enabling SM0, each result was available at the first recorded poll. Final FSTAT is 0x0f000f00, program position is 0, and the comparison passes. One poll establishes availability at that observation; it does not measure transformation latency.

The coordinator recorded 7,316,867,298 ticks at a reported 54 MHz, giving 135.497543 seconds from coordinator entry to terminal snapshot. Loader time and the final journal write/readback are outside that interval. Terminal status is zero; no journal integrity or sequence error was found.

Interpretation and next distinction

This boot meets the declared local-execution, PIO-control and restoration criteria. The uploaded SEIGRASM program ran on RP1 core 0, provided its own return service and configured a connected instruction engine. The stopped/enabled observations distinguish a queued challenge from the subsequent PIO response. Verified upload, program-specific entry, transformed values and stable reports support that execution relation.

Explicit pin selection resolved the prerequisite that stopped the preceding preparation. This establishes an acquisition step beyond application-processor register access. It is one successful boot, with six cases in that boot; it supplies no cross-boot reliability rate or independent electrical waveform measurement.

The next bounded question is whether the same acquisition and resource control recur after a fresh power cycle with a new run identity. That repeat should retain the instruction streams, routing rules and acceptance criteria. Further capability work should identify a documented internal signal connection, establish its controls from the acquired local processor, and recover an observation at the receiving resource. This connects local execution to physical state establishment for the Seigsit. Six PIO cases do not establish six maintained electrical states.

Execution and remaining dependencies

The execution path is authored AArch64 SEIGRASM → direct BSC transfers → RP1 boot ROM entry → authored Cortex-M3 SEIGRASM → authored PIO instructions. The local program owns the polled return service; the application processor owns SD recording. PC tools package literal encodings and independently assess returned records. No foreign target compiler or assembler produces these instruction streams.

SoC boot firmware, RP1 boot ROM, inherited clocks/pads and existing controller transports remain entry dependencies. The experiment replaces the tested RP1 application execution path in volatile memory. It does not establish replacement of all firmware, control of the second local processor, physical Seigsit creation, or sovereignty over the whole cluster. The broader goal includes acquiring those remaining components and connections.

The pin mapping follows the pinned BCM2712 pin tables; volatile entry follows the published RP1 register investigation. The frozen protocol contains the full reference set and exact preparation inputs.

Integrity and provenance

The two read-only acquisitions have SHA-256 2ae2548cbbc6087524547fb04ab7caa9cc6ecc5c450024585d29c39764dad7f0. The prepared image has SHA-256 ff3f8ba8d2787a28e699513e8e6d7763e6350104f81b8c8507276902d71f51e7.

All 29,384 unused journal sectors match their prepared reservations. Partition layout, boot geometry, config.txt and seigr.bin match; the FAT copies agree. Seven sectors outside the journal differ, including System Volume Information. Their writer and timing are not established.