Local execution and PIO control.

Question and rationale

Can SEIGRASM take responsibility for execution inside RP1 and then use its local processor to control PIO? This investigates a specific expansion of control beyond application-processor register access: RP1 PIO control registers are accessible to its local processors but not directly over PCIe.

The objective remains sovereignty over every silicon component and its interconnections, replacement of inherited firmware dependencies, and Hyphos/SeigrOS with native electrical Seigsit relations. The preceding investigation characterized conversion history through application-processor access. Further ADC offset characterization is not an established prerequisite for acquiring local execution. This experiment tests that separate capability.

The proposed connected resource is PIO and its internal transmit/receive path. External pin output is not part of this first trial. A returned transformation would establish local execution and resource control under the stated dependencies; it would not establish a physical Seigsit or six maintained electrical states.

Prepared sequence

1. Initialize the native SD recorder, inventory the AON pin multiplexer, GPIO direction/data and BSC controller. Require function 4 on the RP1 SDA/SCL pins, function 0 on RUN, RUN configured as an output and high, and an idle BSC. Stop before reset on a mismatch.
2. Assert RP1 RUN for 100 ms, release it and wait 100 ms. Access the boot interface at I²C address 0x43; release SYSINFO reset and require component identity 0x20001927.
3. Upload the authored Cortex-M3 instructions, empty local report, six run-specific challenges, four PIO instructions and fault vectors. Compare readback of all 228 four-octet words. Require the local entry marker to remain zero before startup.
4. Write and verify the boot marker, entry address, stack and watchdog reset selection; issue the volatile entry command. Read the entry report through the local program's own polled I²C service at 0x44.
5. Request one PIO trial. The local program checks reset and PIO identity, configures SM0 without external pins or DMA, and loads PULL BLOCK; MOV ISR, ~OSR; PUSH BLOCK; JMP 0. For each of six challenges, require a queued transmit value and empty receive FIFO while stopped; enable SM0 and compare the returned complement. The stopped interval and completion polling are each bounded by 10,000 local iterations, without a calibrated duration claim.
6. Recover the complete 256-octet report twice. Record phase, fault information, processor identity, PIO status and all six cases. Hold RP1 reset after retrieval, record the final state and park the application processor.

The full schedule contains 826 operations and reserves at most 3,295 journal sectors. Each operation records intent, raw result and completion. Failures after the first reset attempt enter the final RUN-reset action. An admission failure before that attempt terminates without asserting reset. A processor or nonreturning register access can leave an incomplete intent; recording failure stops execution.

Execution and dependencies

The target path uses authored AArch64 SEIGRASM for coordination, BSC transactions and SD persistence; authored Cortex-M3 SEIGRASM for local execution and its return channel; and authored PIO instructions for the transformation. PC tools copy literal instruction encodings, construct descriptors and images, and assess returned evidence. No external target compiler or assembler produces these instruction streams.

SoC boot firmware, RP1 boot ROM, existing instruction-set and controller transports, and inherited clock/pad configuration remain apparatus dependencies. The watchdog entry and reset selection draw on the published volatile-entry investigation; their operation on this apparatus remains untested by this return. EEPROM, OTP, PMIC and PLL writes are outside the sequence.

Eleven supplied-response checks passed before installation, covering local execution, PIO controls, upload mismatch, bus failure, missing return service and admission refusal. These checks exercise authored instructions against supplied hardware behavior. They do not establish the board's initial configuration or physical local execution.

Declared criteria

Local execution requires matching upload readback, a zero unstarted marker and a subsequent run-bound entry report with the expected processor identity. PIO control additionally requires all six stopped-engine controls and returned transformations, followed by two matching complete reports. Successful bus transfers alone do not satisfy either criterion. Inaccessible or unattempted stages retain unavailable results.

Preparation and acquisition

Preparation 0F08430A1C7D uses protocol rp1-local-pio-1. All 4,096 installation chunks and two complete readbacks matched before ejection. The prescribed powered interval was five minutes; the returned journal supplies the execution interval below. Total powered duration and physical boot count were not separately measured.

The returned 64 MiB region was read twice without writes. Both captures have the same SHA-256. The protocol and all 24 source inputs remain frozen with the preparation.

Return: admission stopped before reset

Eight valid records contain the inventory, failed admission check and terminal outcome. The inventory read all ten registers. Admission then read 0x107d51070c as 0x00000000; its mask was 0x00000fff and expected value 0x00000044. That first comparison failed. The three remaining admission reads were not attempted; their zero-filled report cells are not measurements.

The coordinator recorded two operation outcomes, zero boot-bus transfers and no reset or access operations. Its terminal snapshot occurred 27,102,483 counter ticks after entry at the reported 54 MHz frequency: 0.501897833 seconds. This excludes loader time and the final journal write/readback. The terminal status is 1, identifying the failed prerequisite; no journal integrity issue was found.

Upload, local entry, PIO trials and report recurrence were not reached. Their outcomes are unavailable. The experiment therefore does not meet its local-execution or PIO-control criteria.

Interpretation and next distinction

The subsequent configured-routing experiment completed local execution and PIO control. The observations below describe the prerequisite failure that motivated that preparation.

The controller map places AON pin control at 0x7d510700. The C0 and D0 pin tables place GPIO0–2 in register 3, yielding the accessed offset 0x0c, with function 4 selecting vc_i2c3 on GPIO0/1. The board wiring description names those pins RP1_SDA, RP1_SCL and RP1_RUN. Both supported revision tables agree on this mapping; the run did not identify the silicon revision.

The observed selector fields are zero, consistent with GPIO mode. The inventory also reports an inactive, disabled BSC and RUN high with its direction field clear. The prepared sequence required the I²C routing to be inherited; it contained no action to establish it. That prerequisite assumption failed. This return does not test whether RP1 accepts uploaded instructions or whether local execution can control PIO.

The next investigation should make the connection configuration an explicit SEIGRASM action: record the initial selector and relevant pin state, admit the documented configuration, select only the SDA/SCL function fields, and verify both the requested fields and preservation of adjacent RUN/SD controls. Only a confirmed route should admit the existing reset, upload and local-execution sequence. Defined cleanup must retain the original routing information. Removing the admission check or repeating the same image would not establish the missing configuration.

This would replace one inherited-configuration dependency with an observed control action. The local processor, PIO and physical Seigsit criteria remain unchanged and unqualified.

Integrity and provenance

The journal identity, sequence, integrity fields, terminal failure and unused reservations match the frozen preparation. The partition table, geometry, config.txt and seigr.bin match; FAT copies agree. Seven sectors outside the journal differ, including System Volume Information. Their writer and timing are not established. These metadata differences do not change the recorded admission outcome.

Capture SHA-256: e1f8723d7851cbc14e49a5f6322092e83d61b0ed6472868b79b5aec761326126. Prepared image SHA-256: afb25da65913e37133d5474ec07b3a64654762d31a1ca5022a50838b74a15e11.