Question and rationale
Can RP1 acquire its internal temperature input and retain observations while the application processor leaves the ADC untouched? Compare stopped operation, one requested conversion and conversion started once in continuous mode. This examines a component-controlled acquisition mechanism within the whole-cluster investigation.
The internal input avoids presuming an undocumented connection between an output and the ADC. The measurement concerns local acquisition and recording. Physical Seigsit establishment, transfer, connected layers and subsequent use require further relations and evidence. The earlier DA9091 exceptions concern another acquisition path and remain unresolved.
Declared method
SEIGRASM enters through the existing boot loader and initializes direct SD recording. Four separately recorded operations check the root-controller route, RP1 identity, ADC clock registers and ADC registers. Each operation has an intent record before access and a completion record after return. The route checks compare live registers with a previously observed configuration; this preparation contains no root-controller or endpoint initialization.
After admission, the prescribed order is stopped, single, stopped, continuous, stopped, continuous, stopped, repeated once: fourteen trials. Each trial requires two matching initial snapshots separated by 1 ms, a disabled converter, an empty disabled FIFO, clear error and interrupt controls, and the existing oscillator selection. It temporarily enables the ADC clock at divisor 1, selects internal input 4, writes ADC DIV 0x00ffff00, enables FIFO error reporting and verifies configuration readback.
The acquisition interval is 2 ms without ADC polling, FIFO reads or SD transactions. After continuous operation is stopped, READY is polled for at most 10 ms. Up to sixteen raw FIFO entries can be retained. An additional 2 ms stopped interval checks for further entries. Configuration restoration precedes SD recording. Bus faults can leave an intent without completion; the exception record resides in RAM and has no guaranteed SD recovery.
The register definitions are drawn from the RP1 ADC driver and clock driver. The board description supplies the nominal oscillator reference. Actual FIFO capacity and conversion cadence remain experimental questions.
Assessment criteria
Admission must succeed before acquisition. Stopped conditions require zero FIFO entries; a single request requires one; continuous operation requires multiple entries without saturation or error. Equal sample values remain valid observations. Configuration restoration and complete chronological recording are assessed separately. Any failed check ends the prescribed sequence and retains the available report.
A complete journal ending in refusal establishes recovery of that refusal. It does not establish completion of the planned acquisition sequence. Unattempted register outputs are represented as unavailable in the analysis, even when their reserved report cells contain zero.
Preparation
Candidate 0E308A2434D1 contains literal AArch64 SEIGRASM, copied into the payload by PC packaging tools. The prepared 64 MiB image reserves up to 141 journal sectors. Eight supplied-response execution and recovery checks passed before installation; two complete SD readbacks matched the image and ejection was recorded. These are preparation checks, separate from this returned record.
The prescribed powered interval was two minutes. The initial ROM/EEPROM loader, CPU instruction encoding, SD transport and PCIe register interface remain apparatus dependencies. This preparation does not replace their firmware or establish a transport without binary dependencies. The frozen protocol preserves the pre-run procedure.
Results: refusal at the root-controller check
Six consecutive records and a terminal refusal were recovered. None of the fourteen ADC trials ran. Both read-only SD captures matched. Candidate identity, record checksums, ordinals, section order and terminal status were valid. The returned executable and boot configuration matched their prepared bytes.
| Observation | Expected | Recorded | Assessment |
|---|---|---|---|
Root identity at 0x1000120000 | 0x271214e4 | 0x271214e4 | Matched |
Command/status at 0x1000120004 | Masked value 0x0002 | Raw 0x00100000; masked value zero | Memory-access prerequisite unmet |
| Remaining root link/window reads | Twenty-one further reads | Not attempted | Unavailable |
| RP1 identity, clock and ADC operations | After route admission | Not attempted | Unavailable |
The command field in the lower half of the second read was 0x0000; the upper status field was 0x0010. The PCI register definitions identify mask 0x0002 as memory-space response enable and status 0x0010 as capability-list support. The returned combined word is not an ADC value or an ADC exception.
The journal records a 54,000,000 Hz counter. From coordinator entry at count 1,931,599 to the terminal snapshot at 23,721,203, 21,789,604 ticks elapsed: approximately 0.403511 seconds. This excludes the final record write/readback and boot-loader time; it is not the measured powered duration. Waiting longer would not advance this invocation after its terminal refusal.
Seven sectors outside the journal changed within the boot volume. The MBR, executable and boot configuration were unchanged, and a System Volume Information directory was present. The capture does not identify the writer or time of those metadata changes.
Interpretation and next decision
The immediate cause of termination is established: the second masked comparison failed. The reason for that initial controller configuration is unresolved. The earlier RP1 route observation recorded memory access enabled; it supplied an example of configured hardware, not a guaranteed entry state for this payload. Current source inspection confirms that the admission routine reads the root configuration and returns on mismatch without initializing it.
This is an implementation gap in the route from entry to RP1. The returned record provides no measurement of PCIe link readiness, current translation windows, RP1 identity, ADC clocking, conversion or FIFO retention. It supports the functioning recorder and the observed root-state refusal. It does not attribute the configuration to competing silicon, firmware interference or the ADC.
The next investigation should inventory the full root-controller state even when memory access is disabled, including link and reset state, translation windows and the route to the intended endpoint. SEIGRASM then needs explicit, state-dependent initialization with before/after observations, bounded waits and restoration where applicable. Command changes must preserve adjacent status semantics. Enabling memory access alone is insufficient without the remaining route checks. The autonomous ADC comparison retains its declared criteria until that path is established.
Evidence and provenance
Preparation identity: 0e308a2434d1cc328bc0962dadc672536bdfeac4d1f6428342b3468664334cbf. Returned capture SHA-256: 8342d54b1e05265daa001c8d90ee0df93e77c1717857a2bc8e18b208aeaf74c8.
The decoder reproduces the failed comparison from the recovered raw values and preserves unavailable reads explicitly. Six return-analysis checks cover provenance mismatch, incomplete recording, inconsistent gate status, unchanged boot files and the distinction between unattempted outputs and measured zero. The final journal record cannot prove its own target readback.
Follow-up: RP1 route activation
Candidate 0B4C3D9D4656 established the route through explicit SEIGRASM updates and reached RP1 identity. Its first ADC trial refused the initial register state before acquisition. The individual experiment and results retain its method, recovered sequence and clock-order hypothesis.