RP1 route activation.

Question and rationale

Can explicit SEIGRASM initialization establish access to RP1 from the controller state supplied at entry, then admit the autonomous ADC comparison? The preceding acquisition attempt stopped with root memory access disabled. Its code checked an existing configuration but did not establish one. This experiment records that entry state and performs the missing initialization.

The component-control investigation develops the capabilities needed to establish and use Seigsit physically. This step tests controller configuration and component access. It does not establish physical Seigsit formation or resolve the earlier DA9091 measurement exceptions.

Method

Following root identity, record all 43 selected root registers before changes. Use individually recorded updates to configure transaction controls, release link reset, select the downstream bus, identify the endpoint, assign its peripheral aperture and establish a four-MiB window from CPU address 0x1c00000000 to bus address 0x80000000. Record complete root and endpoint snapshots again, then check the configured route and RP1 identity.

Each update records its initial value, requested value, readback, access counts and counter interval. Unchanged fields omit the write. PCI command changes use halfword accesses to preserve adjacent status. Counter waits allow 200 microseconds for SerDes settling and 100 milliseconds after link reset release; link polling has a one-second deadline. A bus transaction that never returns is outside that software deadline.

The planned ADC order is stopped, single, stopped, continuous, stopped, continuous, stopped, repeated once. Each trial requires matching initial snapshots and a disabled converter with empty disabled FIFO and clear interrupt controls. The code reads ADC registers before enabling their clock. Acquisition and stopped-retention intervals are each two milliseconds, with no ADC or SD access during those waits. The acquisition method defines the configuration, FIFO criteria and restoration sequence.

All operations have an SD intent before execution, a raw report and a completion record. The schedule contains 61 operations, including 35 configuration, poll or wait operations and fourteen ADC trials, with at most 280 journal sectors. Route configuration remains until power-off; the ADC routine restores its changes when it reaches the modification stage.

Assessment criteria

Route configuration requires matching update readbacks, link readiness, endpoint mapping and RP1 identity. The acquisition comparison additionally requires admitted trials, the prescribed FIFO counts, no acquisition errors and matching restoration. Any failed operation ends the sequence after its report. Snapshot-only operations record raw values without an acceptance mask; a zero status for such a snapshot does not establish that its contents are valid peripheral state.

Complete recording, successful route establishment and completed ADC acquisition are assessed separately. Reserved zero fields after an early refusal are unavailable observations, including acquisition timing, FIFO contents and restoration results.

Preparation and dependencies

Candidate 0B4C3D9D4656 contains literal AArch64 SEIGRASM instructions placed into the image by PC packaging tools. Thirteen supplied-response execution and recovery checks passed before installation. Two complete SD readbacks matched the prepared 64 MiB image. The frozen protocol specifies one two-minute run.

Initial ROM/EEPROM entry, AArch64 execution, SD and PCIe interfaces remain apparatus dependencies. Bridge power, external reset and PHY reference-clock configuration are retained entry conditions; this payload does not initialize all of them or replace component firmware. No external ADC pins, DMA, interrupt enables or persistent firmware writes are used.

Results

163 consecutive records were recovered with a valid terminal refusal. All 47 operations preceding the first ADC trial returned success, including 35 access operations with ten actual configuration writes. The first ADC trial then refused its initial state. The remaining thirteen trials were not attempted.

The first trial is the stopped condition. Its initial CS value fails the implemented 0xfffffeff mask check. Status 1 denotes a busy or unrecognized initial state; these values do not establish a busy converter. The routine returned before its second snapshot, clock enable, conversion request, FIFO draining or restoration. Zero FIFO count and zero restoration mask in its reserved output therefore provide no acquisition or restoration result.

The coordinator counter advanced from 1,931,372 to 357,399,649 at a reported 54,000,000 Hz: 355,468,277 ticks, approximately 6.582746 seconds. This ends at the terminal snapshot and excludes its SD write/readback and boot-loader time. It does not measure the powered duration. Longer waiting would not advance this terminated invocation.

Both read-only SD captures matched. Candidate identity, checksums, ordinals, operation order and terminal consistency passed; the remaining 32,541 journal reservations were unchanged. The MBR, executable and boot configuration matched preparation. Seven other boot-volume sectors changed, with a System Volume Information directory present; their writer and timing are not established.

Interpretation and next investigation

Explicit route initialization succeeded in this boot. The failure boundary moved from the root-controller prerequisite to ADC access. Identity and clock reads demonstrate that RP1 was reachable before the ADC snapshot. Their success does not guarantee continued access after it.

The ADC and clock addresses in the frozen executable agree with the vendor register mapping and clock definitions. The latter identify clock enable as mask 0x0800, clear in the recovered CTRL value. The vendor ADC initialization enables the clock before its ADC register writes. These sources provide register and sequencing references; none is part of the target executable.

Hypothesis: accessing the ADC while its clock is disabled produces an unavailable response and may affect later accesses through the shared path. The changed clock responses make that sequence worth testing. This recording does not establish the origin of 0xdeaddead, a bus timeout, a reset, or interference by another component. There is no root or identity snapshot after the ADC access to localize the change.

The next experiment should enable and verify the ADC clock before the first ADC read. Bracket that first read with independent RP1 identity, clock and root-link observations, recording each address, value and elapsed interval. If access survives, continue with the stopped/single/continuous comparison. Restore and verify ADC settings while its clock is still enabled; restore clock settings last. A failure before the first ADC read would weaken the clock-order explanation; readable ADC state afterward would support that order as a working prerequisite, without proving the exact failure mechanism in this boot.

The supplied-response checks allowed ADC reads with the clock disabled. They therefore did not qualify that physical prerequisite. Their next extension should cover inaccessible peripheral responses and loss of later control reads. No Seigsit formation, transfer or conversion-freshness result follows from this return.

Evidence and provenance

Preparation identity: 0b4c3d9d46561c17a0340a832135a65a02eddae7095bee62db0c3909aff67ab2. Returned capture SHA-256: b0265d9f807f84784c9a438728d5a8811bfc01c4d1904f6da8982b04214e7abe.

Independent raw-field decoding reproduced all 163 records and checked every unused reservation. Ten return-analysis checks cover the two physical returns, unavailable acquisition and restoration fields, inconsistent reports, media provenance, incomplete recording and boot-file identity. A terminal record cannot prove its own target readback.

Clock-before-access investigation

Candidate 8177E25C6B65 enables and verifies the ADC clock before the first ADC read, then records root-link, RP1 identity and clock observations on both sides of that access. Fourteen acquisition trials follow only if admission succeeds. ADC restoration is verified with the clock enabled; a final guarded clock restore retains any original failure.

The returned experiment stopped before ADC access: the clock-enable write read back as 0x10000800, failing the full-register equality check against 0x00000800. Root link and RP1 identity remained readable. Its frozen protocol retains the original criteria; the separate result identifies the register-validation issue and the remaining question.