Timed resident source acquisition.

Question and rationale

Can the measured local timing capability support acquisition from another connected resource while preserving its relation to PIO progression? The preceding resident acquisition stopped before ADC access because its optional cycle counter was unavailable. This investigation retains that source schedule and uses the observed interrupt-disabled SysTick capability, with PIO reference measurements before and after acquisition.

The objective is control of the cluster's components and interconnections as a foundation for Hyphos, SeigrOS and physical Seigsit operation. This run tests local responsibility for acquisition and recording. It does not select one universal time source or an event scheduler.

Method

Authored AArch64 SEIGRASM establishes the recorded boot connection, uploads and verifies Cortex-M3 instructions, and recovers the local journal through the existing return service. One request starts the local sequence. The coordinator allows two seconds without further RP1 transactions, retrieves a header and full report, requests further PIO activity, and retrieves the report again.

The local program admits disabled SysTick controls, selects the processor source with timer interrupts disabled, and verifies progression. A PIO countdown at divider 6 is bracketed by four timer observations around a 4,096-iteration processor loop. The same reference is attempted after acquisition and cleanup. Each reference saves and restores PIO configuration.

The 141-access schedule checks the candidate reset field, disabled ADC clock, divider, selector and register defaults before acquisition. Eight cases cover unchanged and directed source selection in order 0,1,3,2 then 2,3,1,0. Conditions are disabled-to-disabled, disabled-to-enabled, enabled-to-disabled and enabled-to-enabled. Each case establishes its baseline, waits 10,000 local ticks, commands a reference, changes or retains the source, waits another 10,000 ticks, records an untriggered result, then commands two probes.

Each 48-octet record commits its tag, operation, address, request, timer endpoints, before/after observations, status, polling count, final timer control and interval validity. Timing failures and peripheral failures remain separate. Cleanup first writes the candidate reset SET alias, checks that alias, then schedules a direct reset-register check before disabling the ADC clock. A failed cleanup operation stops the remaining cleanup accesses. The outer sequence ultimately holds RP1 RUN low and restores bus routing.

All reported numbers are decimal unless prefixed. Source controls 0 and 1 label this hardware intervention; they do not define Seigsit states. Source-disabled potential and absolute timer frequency remain uncalibrated.

Declared criteria

Require the identified local report, all scheduled accesses, valid intervals, both PIO references, restored timer and peripheral controls, and unchanged observations through a completed later six-case PIO trial. A wrap indication, invalid timer control or reversed endpoints excludes an interval. Failed or missing observations remain in the assessment; ADC error flags and response values do not select replacement readings.

For PIO decrement count D, outer timer bracket O and inner bracket I, conditional relative-rate bounds are max(0,D−1)/(O+1) and (D+1)/(I−1). Multiply by the divider for normalized bounds. These include endpoint quantization under the declared control-bracket assumptions; overlap does not establish independent oscillators or absolute accuracy. The frozen protocol preserves the complete preparation and criteria.

Preparation and recovery

Preparation 83841979437C preserves 40 source inputs and 24 passing preparation checks. Installation verified all 4,096 transfers and two full image readbacks before ejection. The procedure allowed 25 minutes powered. No independent measurement of total powered duration or physical boot count accompanies this return.

The return contains all 29,498 journal sectors, 7,378 outer operations and 7,362 boot-bus transfers. All 1,469 uploaded words matched their readbacks. The coordinator interval was 1,219.119409 seconds (20 minutes 19.119 seconds) at its reported 54 MHz, excluding boot-loader time and the final record write/readback. This interval primarily includes upload and report recovery; it is not the duration of local ADC acquisition.

Local source responses

All eight source cases completed, including 24 commanded conversions and eight untriggered readings. The initial six PIO controls passed. Local execution committed 135 access records: 134 successful acquisition accesses and one failed cleanup comparison. All 135 recorded timing intervals were valid; no wrap or invalid-control indication was recorded. No ADC error indication was retained in the recorded case controls.

Both enabling cases changed by +115 counts. Both disabling cases changed by −115 and −114 counts in their two probes. All eight untriggered readings retained the preceding reference. The first disabled-source reference was 772 before subsequent readings of 748; that 24-count departure remains recorded. Its cause is unresolved. Later unchanged-source observations varied by zero or one count.

All 16 requested waits recorded 10,090 ticks between their access endpoints. Recorded access intervals ranged from 151 to 10,090 ticks. Every conversion-readiness poll matched on its first recorded read. This establishes the recorded readiness and result sequence; it does not independently resolve analog conversion freshness.

PIO references across acquisition

Both references passed their timing, progression, snapshot and diagnostic checks. Divider-normalized bounds are 0.999558632 to 1.000557997 in each reference, containing 1. These bounds overlap the previous local-time result. Exact counts should not be equated across those programs: their instruction sequences differ. Timer controls and reload returned to their initial zero values; the original timer phase is not restorable.

Cleanup verification boundary

The terminal header reports phase 3, primary status 0, cleanup status 1 and last tag 134. That operation wrote 0x00000001 to reset SET alias 0x40016000. Both reads of that address returned zero, so the authored comparison expecting one failed. The next direct check at 0x40014000, tag 135, was not executed. The remaining five cleanup operations, including clock disable and full reset-bank comparison, were also not reached.

The same return provides a control for interpreting that failure. At tag 7, reset CLR alias 0x40017000 also read zero before and after its write. At tag 8, the direct register changed from 0xf631efff to 0xf631effe, confirming the intended field cleared. Thus zero at an alias does not, by itself, establish an ineffective write. Whether the later SET write restored the field remains unobserved. The specific failed assumption was that the SET-address readback would expose the asserted field.

Both complete 7,168-octet reports and the early header agree. The later-PIO activity marker remained zero because phase 3 declined that command. Its unchanged final PIO report cannot establish a new six-case trial. The declared retention-through-later-activity criterion is therefore not met, despite matching recovered contents. The second timing reference did execute after the cleanup comparison, and outer RUN reset and route restoration completed.

Interpretation and next investigation

Project-authored execution inside RP1 now controls the source comparison and records its observations locally with usable timing. PIO progression remains compatible with the measured processor-time relation across that work. Expected register defaults and completed source responses following selective reset release support the candidate ADC-reset association, without establishing every effect of that reset field.

The next investigation should verify reset action through the direct register, retaining SET/CLR alias reads as separate observations. Confirm the field and full bank after assertion, then verify clock restoration and subsequent PIO reuse. Keep the source cases and timing references fixed so the cleanup interpretation is the changed relation. Include a supplied-response check where an alias reads zero although the direct register changes. This discriminates an ineffective reset write from a readback assumption; an unchanged rerun cannot make that distinction.

The direct-reset comparison subsequently completed all 141 local accesses, confirmed reset and clock restoration, and retained its acquisition records through further PIO activity. It preserves the same target instructions, source cases and timing references, changing only the tag 134 comparison mask.

The source-off initial departure also warrants a later acquisition-history comparison with matched first-use controls. It should not be removed as settling noise or mixed with this cleanup question. Six calibrated electrical states, physical native Seigsit transport, absolute/ERA time anchoring and control of every cluster component remain open. SoC boot firmware, RP1 ROM entry, inherited clocks/pads and current return transports remain dependencies. This work adds a measured local acquisition capability toward replacing those dependencies.

Evidence and provenance

The SD was read twice without writes. Both 64 MiB captures have SHA-256 c5b1ead42880c6c52124bf86ae5f69807f542ae3eb782ce4981f084063001842. All 49 preparation artifacts verify. The 3,206 unused journal sectors match their prepared reservations. Partition geometry, boot configuration and executable are unchanged; FAT copies agree. Seven sectors outside the journal changed, including directory metadata. Their writer and timing are not established.

Eighteen return-assessment checks passed, covering physical records, response values, exact timing bounds, the cleanup stop, missing fragments and rejection of unsupported retention claims. The original target and preparation reader remain frozen. The current return reader exposes acquisition availability, individual valid intervals and the cleanup outcome separately; no physical criterion was relaxed.

Implementation and recording contract · Preceding timing observations · Preceding acquisition prerequisite.