Local time relationships.

Question and rationale

Can SEIGRASM establish and measure several related progressions within RP1, preserve their state through pauses and rate changes, and retain the observations while reusing the controlled resource? Seigr time is intended to connect scales serving different purposes, including Noesis. The unfinished spacetime4d reference relates temporal coordinates, phase and uncertainty to spatial coordinates. This experiment investigates a physical prerequisite for that development.

The preceding resident return recorded an unavailable optional cycle counter and stopped before ADC access. This investigation measures an available local timer alongside our own PIO instruction stream. Timer admission is assessed separately from PIO progress; a timer failure preserves the PIO observations. No universal SeigrOS tick or event scheduler is selected.

Method

Authored AArch64 SEIGRASM establishes the verified RP1 boot connection, uploads and verifies project-authored Cortex-M3 and PIO instructions, and recovers the local reports. A single request starts the 36-case comparison; all cases execute locally before bulk retrieval. The application processor allows two seconds without further RP1 transactions, retrieves a compact header and the full journal, requests a further six-case PIO transformation, then retrieves the journal again.

The local program admits SysTick only when enable and interrupt-enable controls are clear. It saves controls and reload, selects the processor clock with interrupts disabled, loads the maximum countdown and verifies progress. An authored one-instruction PIO countdown uses state machine 0. Each case snapshots its X register while stopped, selects and verifies divider 1, 6 or 36, restarts divider phase, and executes either a stopped control, a running PIO with a decrement-only processor loop, or a running PIO with an arithmetic processor loop.

Two workload lengths, 256 and 4,096 iterations, produce 18 combinations. The second block reverses their order. X is initialized once and preserved between cases. Four local-timer readings bracket PIO enable and stop writes, with completion barriers. Each committed record contains case identity, X endpoints, four timer endpoints, status and diagnostic controls, divider readback and arithmetic result. All numerical measurements on this page use decimal unless prefixed.

Saved timer controls/reload and PIO configuration/instruction are restored and read back. SysTick CURRENT is write-clear: the original counter phase cannot be restored. PIO scratch state is not restored. The outer cleanup holds RP1 RUN low and restores bus routing. The local comparison makes no ADC, PMIC, PLL, GPIO pin-assignment, DMA or timer-interrupt configuration change.

Declared criteria

Require complete identified records; unchanged stopped X; positive running progress; continuity between cases; valid workload results; matched divider readbacks; clear selected PIO diagnostics; restored configuration; and a matching early header. Retention requires unchanged observations through a completed subsequent PIO trial. Only its declared activity marker may change.

A timing interval requires admitted timer progress, the selected control value, descending samples and a clear wrap indication. A wrap or reversed samples invalidate that interval; the reader never estimates a missing wrap count. For decrement count D, outer bracket O and inner bracket I, relative-rate bounds are max(0,D−1)/(O+1) and (D+1)/(I−1). The endpoint allowance is one count in each progression. Divider-normalized bounds multiply both limits by the selected divider.

These are conditional measurement bounds, not statistical confidence intervals. They assume the effective PIO enable/stop changes lie inside the recorded control brackets. Peripheral-internal application latency remains unresolved. Compatibility with a common normalized rate is assessed separately from complete execution, and does not prove oscillator independence.

Preparation

Preparation 1C4778884786 preserves 32 source inputs. All 47 preparation checks passed. The outer schedule contains 3,055 operations, 628 uploaded words and at most 12,206 SD journal sectors. The local report is 2,464 octets: a 128-octet header, 36 records of 64 octets, and a 32-octet trailer. Installation verified 4,096 chunks and two complete image readbacks before ejection. The prescribed powered interval was 15 minutes; completion is determined from the recovered records.

Return: related local progressions

All declared execution, timing and retention criteria passed in this boot. The return recovered all 12,206 journal sectors, all 3,055 outer operations and 3,039 boot-bus transfers without a reported transport failure. All 628 upload readbacks matched. The local report records phase 2, status 0 and 36 committed cases. SysTick changed from disabled controls to 0x00000005; admission samples descended from 16,777,166 to 16,777,135.

The corresponding inner/outer timer intervals are 5,411/5,477 ticks for the short decrement loop, 7,217/7,283 for short arithmetic, 86,051/86,117 for the long loop and 114,737/114,803 for long arithmetic. They are identical across dividers and repeated orderings. More processor work increased both the elapsed local ticks and concurrent PIO progress.

Every running case includes 1/divider within its relative-rate bounds. All 24 divider-normalized intervals share 0.999695133 to 1.000305048, rounded from exact limits 114769/114804 and 114771/114736. Thus a normalized ratio of 1 is compatible with all observed cases. This does not assign either progression an absolute frequency.

The coordinator interval was 504.787422 seconds (8 minutes 24.787 seconds), from 27,258,520,811 ticks at the reported 54 MHz. It includes upload and report recovery, excludes boot-loader time and the final record write/readback, and is not the duration of the local comparison. No independently measured total powered duration or physical boot count is available.

Interpretation and next investigation

Project-authored execution now controls a local progression, changes its rate, pauses it without losing its accumulated state, measures its relation to processor timing, and retains those measurements through resource reuse. This supplies an observed connection between time scales and an available timing capability for local acquisition. Processor workload changes elapsed ticks; PIO divider changes its relative progression. Neither operation requires timer interrupts in this implementation.

The two reversed blocks establish within-boot recurrence under the tested conditions. They do not establish recurrence across boots, longer-duration stability, absolute accuracy, separate oscillator ancestry, or a conversion from these counters to Earth rotation angle. The unused final two trailer words contain unspecified SRAM and have no diagnostic meaning; their recovery does not make them measurements.

The timed resident acquisition return applies this capability to another connected resource: eight source cases and 24 commanded conversions completed with valid recorded timing. PIO references agree before and after acquisition. A reset SET-alias comparison stopped cleanup before direct confirmation; the direct-reset comparison subsequently verified restoration and retained acquisition records through further PIO activity.

Further time investigations can then test longer intervals and additional clock references while preserving each source's scope and uncertainty. These results do not establish an operative Noesis, physical native Seigsit or sovereignty over the complete cluster. SoC boot firmware, RP1 ROM entry, inherited clocks and the current recording/return transports remain dependencies to resolve.

Protocol and provenance

The 64 MiB return was read twice without writing to the SD. Both SHA-256 hashes are a1fdd46589c7ed8f1a58b5e24315f32543612b0fcb1d850f17be5a85fb76cb57. All 41 frozen preparation artifacts verify. All 20,498 unused journal sectors match their prepared reservations. Partition geometry, boot configuration and executable are unchanged; the FAT copies agree. Seven sectors outside the journal differ, including System Volume Information. Their writer and timing are not established.

Register and instruction references: Cortex-M3 Technical Reference Manual, SysTick; RP1 PIO registers; PIO instruction encodings. SEIGRASM implementation · Earlier acquisition timing.