Question and rationale
Can SEIGRASM inside RP1 control a source-response investigation, retain its own observations, and preserve them through subsequent PIO activity? The configured-route return established local execution and PIO control. Earlier source-response observations and acquisition-history results provide relations to investigate under local control.
The contribution to silicon sovereignty is local responsibility for an observable process, including configuration, timing, recording and recovery. The broader objective includes acquiring the remaining components and their interconnections and establishing the physical Seigsit.
Method
Repeat the verified upload, entry and PIO controls. A single request then starts the resident acquisition. The local program admits a progressing DWT counter, establishes the ADC clock and tests one candidate reset selection. Eight cases in two reversed blocks compare source activation, deactivation and unchanged-source controls. Each case retains a reference, an untriggered reading and two subsequent probes: 24 commanded conversions in total.
The application processor leaves a two-second interval without RP1 transactions, then retrieves the local journal. A further PIO trial tests retention before the second retrieval. The journal records requested operations, raw before/after observations, counter intervals, statuses and polling counts. Failures and ADC error flags remain visible. Local cycles are not converted to calibrated time.
Reset-bank-zero field zero is an ADC-selection hypothesis, not an established identification. The test releases only that field and checks register defaults and conversion behaviour. Unexpected prerequisites stop the trial. Cleanup holds the candidate peripheral in reset before disabling its clock; the established outer cleanup holds RP1 RUN low and restores SDA/SCL routing.
Declared criteria
Assess complete local execution, source-response observations, error flags, cleanup and journal retention separately. Require independent reconstruction of the declared access order and outcomes. For retention, require a completed subsequent PIO trial and unchanged acquisition records; only the declared activity marker changes. Preserve partial cases, first readings, equal results and unexpected amplitudes. The frozen protocol fixes the complete procedure and assessment.
Preparation
Preparation 17F045422EE2 contains 31 frozen source inputs. All 33 preparation checks passed, including authored instructions with supplied peripheral responses, complete SD recovery and earlier physical-return regressions. The native table has 141 accesses; the outer schedule has 6,296 operations and a maximum of 25,170 SD journal sectors. Installation verified 4,096 chunks and two complete readbacks, then ejected the SD.
The prescribed powered interval is 25 minutes, allowing for verified upload and two recoveries of the detailed local journal to SD. Completion is determined from the returned records.
Return: counter admission
The resident acquisition criterion was not met. All 6,296 outer operations and 25,170 journal sectors were recovered, including 6,280 boot-bus transfers without a reported transport failure. All 1,294 uploaded words verified. The local-entry report, six initial stopped/running PIO cases and their repeated report passed. The resident program then entered and stopped before its first scheduled peripheral access.
| Observation | Recorded value | Interpretation |
|---|---|---|
| Resident entry | Marker 0x524c4a31; phase 3; status 10 | The program entered and returned its counter-admission failure. |
| Counter capability | DWT_CTRL = 0x4f000000 | NOCYCCNT is asserted: the requested cycle counter is not supported. |
| Access progress | 0 of 141 scheduled accesses; cleanup-entered marker 0 | No candidate reset, ADC clock or ADC access was reached. All eight cases remain unobserved. |
| Control restoration | DWT control 0x4f000000; DEMCR 0x00000000 | Both restored readbacks match their original observations. |
| Report recovery | Two identical 5,768-octet resident reports with the correct run identity | The failure header remained recoverable. The cleared record region contains no acquisition observations. |
| Subsequent PIO | Activity marker remains 0; final PIO report equals the initial completed trial | The local handler declined the additional trial because acquisition had failed. Retention through subsequent PIO activity was not tested. |
| Outer cleanup | Routing restored; direction and SD outputs preserved; RUN held low | Connection cleanup completed. Recorded local fault fields remain zero. |
The saved control value and authored instruction path identify the failure before counter enable and progress sampling. Their zero-filled header cells are not observations of a stationary counter. The Cortex-M3 Technical Reference Manual, section 11.5.1, Table 11-7, defines the unavailable-counter indication; the return records it directly.
The coordinator interval is 1,040.367983 seconds (17 minutes 20.368 seconds), from 56,179,871,057 ticks at a reported 54 MHz. This includes upload, requests and bulk recovery, and excludes loader time and the final record write/readback. It is not the duration of resident acquisition. Total powered duration and physical boot count were not independently measured.
Interpretation and next investigation
Local entry and the initial six PIO comparisons recur after the preceding successful boot, with a new identity and a larger upload. The resident failure report shows that project-owned execution can identify an unavailable capability, preserve the reason locally and return it without losing the connection. The ADC-selection hypothesis and source-response comparison remain untested.
The implementation made acquisition depend on an optional cycle counter. The next investigation, Local time relationships, compares an authored PIO progression with interrupt-disabled SysTick across divider, workload and pause changes. Timer availability is assessed separately; a missing timer preserves the PIO observations. The experiment supports interconnected time scales without selecting a universal SeigrOS clock or event scheduler. A loop count alone is not reported as elapsed time.
The prepared comparison recovers a compact header before its detailed observations, bounds relative rates using control brackets and endpoint quantization, restores saved configuration and tests subsequent PIO use. Its 36 cases and reversed order examine local relationships; clock independence, absolute frequency and an ERA anchor remain unresolved. ADC source-response work can use a subsequently qualified timing capability. The returned comparison completed all 36 cases with valid intervals and retained observations through subsequent PIO activity.
This return does not establish physical Seigsit states, power-loss persistence, independent analog conversion freshness or sovereignty over the complete cluster. SoC boot firmware, RP1 ROM entry, inherited clocks/pads and the return transport remain dependencies. Local acquisition and retention remain steps toward controlling connected resources for the physical Seigsit.
Protocol and provenance
The 64 MiB return was acquired twice using read-only access. Both SHA-256 hashes are d4fcc0136f6c8e5035a4d52a3de9deae147ec27e8d96d6daf311d6b01fcd7eeb. All 7,534 unused journal sectors match their prepared reservations. Partition geometry, boot configuration and executable match the preparation; both FAT copies agree. Seven sectors outside the journal differ, including System Volume Information. Their writer and timing are not established.
Timer register semantics: Cortex-M3 Technical Reference Manual, section 8.2.2. SEIGRASM implementation · Preceding physical result.