Clocked RP1 ADC access.

Question and rationale

The three-cycle clock-control experiment established accepted enable/disable readbacks and final restoration without ADC access. An earlier route-activation return recorded 0xdeaddead from ADC registers after initially observing a disabled clock. This investigation asks whether one ADC control/status read returns after clock enable, whether its surrounding controls remain readable and whether the clock can subsequently be restored.

This is a component-access prerequisite for the intended Seigsit foundation. Access, conversion and physical Seigsit creation remain separate experimental claims.

Method

Retain the established route and require initial clock CTRL=0, DIV=1 and SEL=1. Enable the clock through SEIGRASM access kind 5, separating writable mask 0x0800 from observed-field mask 0x10000000. Wait at least one millisecond. Individually record root link, root command, RP1 identity and clock CTRL/DIV/SEL; repeat the unchanged clock request and check admission.

Operation 62 reads one four-octet value from ADC CS at RP1 + 0x000c8000. Preserve the response without imposing an expected value. Record the same six surrounding controls, check admission again, then clear clock enable through guarded restoration and record final controls. No ADC register write, conversion request, READY polling or RESULT/FIFO access is scheduled.

The sequence contains 79 operations, each with persisted intent, report and completion. Clock enable is operation 52; the before/after observations occupy 54–59 and 63–68. Restoration is operation 73 and the final check is 78. A completed failure after enable enters cleanup; a recording failure stops further operations. An unresponsive bus transaction cannot be interrupted by the existing counter deadline.

Assessment criteria

Assess read recovery, surrounding controls and restoration separately. A recovered zero is a value; a missing report remains unavailable. Retain a repeated 0xdeaddead response as the previously observed pattern without assigning undocumented meaning. Sequence acceptance requires the declared route/control checks and restoration; it does not qualify the ADC response or prove conversion.

Preparation and dependencies

Candidate D37014D92559 retains all eight target SEIGRASM instruction sources from the preceding clock-control candidate. New descriptors select existing read, control, wait, admission and recording operations. Twenty-one supplied-response execution checks passed, including zero, the prior unavailable pattern, access loss, unrelated clock fields and recording failure after the ADC read. Both complete installation readbacks matched preparation. The frozen protocol specifies a two-minute powered interval.

Existing ROM/EEPROM entry, AArch64 execution, processor counter, SD and PCIe transport, retained bridge power/reset/reference-clock configuration and existing RP1 firmware remain apparatus dependencies. The dormant ADC acquisition routine has no callable descriptor in this run. The experiment does not replace firmware or create or transport a physical Seigsit.

Results

All 250 consecutive records and 79 operations were recovered with accepted completion. The single ADC CS read returned 0x00000000, with one read, zero writes and completed intent/report/completion records. The previous 0xdeaddead pattern was absent from this response.

Clock enable wrote 0x00000800 and read 0x10000800. The repeated unchanged request performed one read and no write. Restoration performed one write of zero and read zero; its later CTRL observation remained zero and the final control check passed. No ADC acquisition trial was attempted.

The ADC access routine spanned 73 ticks at the recorded 54 MHz counter frequency, approximately 1.35 microseconds. The first later control read began 6,253,591 ticks, 115.807 milliseconds, after that routine ended. The ADC read began 1.169894 seconds after the clock-enable routine ended. Those intervals include intervening recording and control operations; they do not measure conversion or clock settling.

The coordinator recorded 535,840,799 ticks, 9.922978 seconds, from entry to its terminal snapshot. This excludes boot-loader time and terminal SD write/readback. The terminal report records index 78, status zero and 79 completed operations.

Acquisition and recording integrity

Two complete read-only 64 MiB acquisitions matched exactly. Independent reconstruction verified journal identity, all checksums, senary fields, ordinals, the ADC intent/report/completion sequence and terminal counts. All 32,454 unused reservations matched preparation.

The MBR, executable and boot configuration were unchanged. Seven other boot-volume sectors differed and a System Volume Information directory was present; the writer and timing remain unestablished. No SD write was performed during acquisition. Exact powered duration was not independently measured; returned counters delimit the recorded sequence.

Interpretation and next investigation

The clocked ADC read returned and subsequent component access and clock restoration remained usable in this boot. Zero is a recovered control/status response, not an absent record or an analog measurement. The vendor register definitions identify distinct converter-enable and READY fields; zero asserts neither. These definitions inform the next intervention, without proving that this response alone establishes converter operation.

The difference from the earlier unavailable pattern supports clock-before-access initialization as a working hypothesis. The recordings come from different boots and access sequences, so they do not isolate clock enable as the sole cause. No acquisition, conversion freshness, analog accuracy, firmware exclusion or physical Seigsit transport was demonstrated.

Next investigation: retain this clocked access sequence, snapshot the ADC configuration, and test a bounded converter-enable/READY transition. If admission and readiness succeed, request one conversion of the internal input and preserve status, raw result, timing and restoration. Include an untriggered observation for comparison. Failure must retain its exact stage and surrounding controls. This tests whether the accessible block responds to a controlled conversion request before extending autonomous acquisition.

Evidence and provenance

Preparation identity: d37014d92559ca44b1caac3454abde9c2828e1ea462f6b807498fda015505a00. Returned capture SHA-256: a1bd9ecc233377c4ed5e334e125ca72809792db7d7de6a9e4166628afe0c2b08.

Twenty-four return-analysis checks cover the five preserved RP1 returns. The new checks independently reconstruct the zero response, distinguish it from a missing report, retain before/after controls and restoration, and reject altered read contracts. The terminal record cannot establish its own target readback.